Field-Programmable Gate Arrays

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Xilinx System Generator Error!

Hi, I am trying to port my VHDL design code into System Generator "Black Box" with some I/O Buffer instatiated, which i...
0 comments posted 19yrs
posted by james.lbs
0 comments posted 19yrs posted by james.lbs

overloading ' operators in VHDL

Hello, I know that it is possible to overload operators like 'and', 'or', '+',... by using a function with the name "an...
2 comments posted 19yrs
posted by Karel.Deprez
2 comments posted 19yrs posted by Karel.Deprez

Opening for Senior Level Design Test Engineer

Hi Friends We are having urgent requirement for Senior Level Design Test Engineer for our client in Bangalore. Job Loca...
0 comments posted 19yrs
posted by ram.addepalli
0 comments posted 19yrs posted by ram.addepalli

Urgent requirement for Sr.Engineer (Verification)

Hi Friends We are having urgent requirement for Sr.Engineer (Verification) for our client in Bangalore. Job Location: B...
0 comments posted 19yrs
posted by ram.addepalli
0 comments posted 19yrs posted by ram.addepalli

Excellent Opening For ASIC Design Engineer !!!!!

Hi Friends We are having urgent requirement for Sr. Asic Design Engineer for our client in Bangalore. Job Location: Ban...
0 comments posted 19yrs
posted by ram.addepalli
0 comments posted 19yrs posted by ram.addepalli

project in chennai

dear friends i have projects for freelance and others contact snipped-for-privacy@yahoo.com
0 comments posted 19yrs
posted by thiagacp44
0 comments posted 19yrs posted by thiagacp44

XAPP851 fifo36 missing

I need the FIFO36 entity for XAPP851 (DDR SDRAM Controller Using Virtex-5 FPGA Devices). Either it wasn't in the zip fil...
3 comments posted 19yrs
posted by bradsmallridge
3 comments posted 19yrs posted by bradsmallridge

Ethernet Code Problem with Xilinx Spartan3E

I'm trying to get a Spartan3E FPGA to communicate with a PC. I'm using lwIP and Microblaze and have managed to get the...
1 comments posted 19yrs
posted by calkins
1 comments posted 19yrs posted by calkins

Altera + ARM Cortex-M1

Could we expect the same step from Lattice? Or Xilinx will come with this possibility sooner? http://www.altera.com/pro...
0 comments posted 19yrs
posted by vitek.vitek
0 comments posted 19yrs posted by vitek.vitek

VHDL Design Pattern Book

After reading http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/d33ee4b046fdbc83/3c6a335982d8fccd#3c6a335...
1 comments posted 19yrs
posted by erik.k.anderson
1 comments posted 19yrs posted by erik.k.anderson

Command line quartus_pgm very slow

Hi folks, I have a question regarding the use of the command line quartus programmer tool under Linux. I have been usin...
1 comments posted 19yrs
posted by sderrienREMOVE
1 comments posted 19yrs posted by sderrienREMOVE

ML410 Board & 1GB DDR2 DIMM Problem

Hi - I'm having problems getting a 1GB DDR2-667 DIMM to work with an ML410 board. I'm working with the plb_ddr2 IP core...
3 comments posted 19yrs
posted by werneta
3 comments posted 19yrs posted by werneta