Field-Programmable Gate Arrays

Opening for Senior Level Design Test Engineer

Hi Friends We are having urgent requirement for Senior Level Design Test Engineer for our client in Bangalore. Job Loca...

0 comments posted 18yrs

posted by ram.addepalli

0 comments posted 18yrs posted by ram.addepalli

Urgent requirement for Sr.Engineer (Verification)

Hi Friends We are having urgent requirement for Sr.Engineer (Verification) for our client in Bangalore. Job Location: B...

0 comments posted 18yrs

posted by ram.addepalli

0 comments posted 18yrs posted by ram.addepalli

Excellent Opening For ASIC Design Engineer !!!!!

Hi Friends We are having urgent requirement for Sr. Asic Design Engineer for our client in Bangalore. Job Location: Ban...

0 comments posted 18yrs

posted by ram.addepalli

0 comments posted 18yrs posted by ram.addepalli

Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)

I'm trying to do something I think should be simple. I've seen several posts about building custom jtag programmers usi...

8 comments posted 18yrs

posted by cepope

8 comments posted 18yrs posted by cepope

project in chennai

dear friends i have projects for freelance and others contact snipped-for-privacy@yahoo.com

0 comments posted 18yrs

posted by thiagacp44

0 comments posted 18yrs posted by thiagacp44

XAPP851 fifo36 missing

I need the FIFO36 entity for XAPP851 (DDR SDRAM Controller Using Virtex-5 FPGA Devices). Either it wasn't in the zip fil...

3 comments posted 18yrs

posted by bradsmallridge

3 comments posted 18yrs posted by bradsmallridge

Ethernet Code Problem with Xilinx Spartan3E

I'm trying to get a Spartan3E FPGA to communicate with a PC. I'm using lwIP and Microblaze and have managed to get the...

1 comments posted 18yrs

posted by calkins

1 comments posted 18yrs posted by calkins

Altera + ARM Cortex-M1

Could we expect the same step from Lattice? Or Xilinx will come with this possibility sooner? http://www.altera.com/pro...

0 comments posted 18yrs

posted by vitek.vitek

0 comments posted 18yrs posted by vitek.vitek

VHDL Design Pattern Book

After reading http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/d33ee4b046fdbc83/3c6a335982d8fccd#3c6a335...

1 comments posted 18yrs

posted by erik.k.anderson

1 comments posted 18yrs posted by erik.k.anderson

precision errors. microblaze vs matlab single precision... huh?

Hi all embedded gurus out there, I am working on an embedded platform using microblaze. I am trying to implement an alg...

0 comments posted 18yrs

posted by chrisdekoh

0 comments posted 18yrs posted by chrisdekoh

Command line quartus_pgm very slow

Hi folks, I have a question regarding the use of the command line quartus programmer tool under Linux. I have been usin...

1 comments posted 18yrs

posted by sderrienREMOVE

1 comments posted 18yrs posted by sderrienREMOVE

[Nios II] How fast the cpu in Nios II can reach in the Cycone ?

Can it reach 100 DMIPS =A3=BF I give the cpu 100MHz clk, and use the Fast Core. There is a program: void main() { while...

3 comments posted 18yrs

posted by hezhikuan2007

3 comments posted 18yrs posted by hezhikuan2007

ML410 Board & 1GB DDR2 DIMM Problem

Hi - I'm having problems getting a 1GB DDR2-667 DIMM to work with an ML410 board. I'm working with the plb_ddr2 IP core...

3 comments posted 18yrs

posted by werneta

3 comments posted 18yrs posted by werneta

Address sensitive process, Xilinx virtex2pro

hi, i'm trying to write a process that is sensitive to a given address, i wrote something like this: my_proc: process (B...

9 comments posted 18yrs

posted by yoni.lan

9 comments posted 18yrs posted by yoni.lan

FPGA Archives

How do you get messages from comp.arch.fpga archives? Google brings up headings that I may want to read, however, when...

5 comments posted 18yrs

posted by bradsmallridge

5 comments posted 18yrs posted by bradsmallridge