Field-Programmable Gate Arrays

Good VHDL reference?

It seems I have misplaced my VHDL book a long time ago and I can't figure out where I left it. In short: I need a new V...

7 comments posted 18yrs

posted by nico

7 comments posted 18yrs posted by nico

PCI byte enalbes in read cycles

Hi all, I'm implementing a PCI interface in FPGA, but I'm stuck trying to figuring out what happens with byte enables i...

13 comments posted 18yrs

posted by isd_mod

13 comments posted 18yrs posted by isd_mod

Stratix III Memory usage efficiency

Has anyone else encountered the problem of shape and size of M9K blocks (I suppose this applies to other devices also)....

6 comments posted 18yrs

posted by David.Wooff

6 comments posted 18yrs posted by David.Wooff

application about hardeware attributes

Hi everyone, I'm a student of the RWTH (or university of) Aachen, Germany. Right now I'm writing my diploma thesis at t...

1 comments posted 18yrs

posted by diplom

1 comments posted 18yrs posted by diplom

microblaze toolchain compilation question

hello all, I'm trying to compile the microblaze-toolchain from source on a 64 bits linux system, but got stuck. The sou...

2 comments posted 18yrs

posted by tralalal

2 comments posted 18yrs posted by tralalal

hydraxc

hi i have a question. is there a xbd file (for edk) for the hydraxc available? and where can i find some documentation...

0 comments posted 18yrs

posted by u_stadler

0 comments posted 18yrs posted by u_stadler

Xilinx core generator MIG module generates a slow timing for a DDR2 SDRAM controller

Hello. I've used the Xilinx core generator MIG module to generate a DDR2 SDRAM controller. The design supports generics...

4 comments posted 18yrs

posted by damicha

4 comments posted 18yrs posted by damicha

ACM SAC 08: DEADLINE EXTENSION (16 Sept, 2007)

SUBMISSION DEADLINE: September 16th, 2007 SUBMISSION SITE: http://sac.cs.iupui.edu/SAC2008/ CALL FOR PAPERS - SAC 2008...

0 comments posted 18yrs

posted by ronaldomenezes

0 comments posted 18yrs posted by ronaldomenezes

Uses of Gray code in digital design

Hello, Most books on digital design discuss Gray codes. However, most of the focus is on generating these codes, rather...

56 comments posted 18yrs

posted by richard.melikson

56 comments posted 18yrs posted by richard.melikson

Question about Virtex-4 DCM

I have an application where I need to model a circuit that has two power rails. A Vitrex-4 has only one internal power...

2 comments posted 18yrs

posted by ghelbig

2 comments posted 18yrs posted by ghelbig

1/2 Convolutional Encoding of CNAV Data

Does anyone know how to implement a 1/2 (1 binary bit in, 2 out, message length of 7) convolutional encoder in HDL? I a...

0 comments posted 18yrs

posted by amitpatel130

0 comments posted 18yrs posted by amitpatel130

What is called carry chain structure in FPGA is called in IC?

Hi, I want to know what is called carry chain structure in FPGA is called in IC? Thank you. Weng

6 comments posted 18yrs

posted by wtxwtx

6 comments posted 18yrs posted by wtxwtx

What is the name of Altera latest and most advanced chip serial that is competable in technology with Vertex V in terms of system strucute(LUT6...)

Hi, I would like to know what is the name of Altera latest and most advanced chip serial that is competable in technolo...

2 comments posted 18yrs

posted by wtxwtx

2 comments posted 18yrs posted by wtxwtx

VHDL Synthesis Error

Hello all, I am trying to implement a network adapter that sends small packets to and from FPGA boards using VHDL. I wa...

4 comments posted 18yrs

posted by ray.delvecchio

4 comments posted 18yrs posted by ray.delvecchio

LVDS pin placing on CYCLON II problem

Hi, I'm working on design with LVDS signals and when I'm trying to place LVDS inputs at dedicated pins I got : Error: N...

3 comments posted 18yrs

posted by gorskia

3 comments posted 18yrs posted by gorskia