Latest threads in Field-Programmable Gate Arrays

Address sensitive process, Xilinx virtex2pro

hi, i'm trying to write a process that is sensitive to a given address, i wrote something like this: my_proc: process (B...

9 19yrs

yoni.lan

9 19yrs yoni.lan

FPGA Archives

How do you get messages from comp.arch.fpga archives? Google brings up headings that I may want to read, however, when...

5 19yrs

bradsmallridge

5 19yrs bradsmallridge

Good VHDL reference?

It seems I have misplaced my VHDL book a long time ago and I can't figure out where I left it. In short: I need a new V...

7 19yrs

nico

7 19yrs nico

PCI byte enalbes in read cycles

Hi all, I'm implementing a PCI interface in FPGA, but I'm stuck trying to figuring out what happens with byte enables i...

13 19yrs

isd_mod

13 19yrs isd_mod

Stratix III Memory usage efficiency

Has anyone else encountered the problem of shape and size of M9K blocks (I suppose this applies to other devices also)....

6 19yrs

David.Wooff

6 19yrs David.Wooff

application about hardeware attributes

Hi everyone, I'm a student of the RWTH (or university of) Aachen, Germany. Right now I'm writing my diploma thesis at t...

1 19yrs

diplom

1 19yrs diplom

microblaze toolchain compilation question

hello all, I'm trying to compile the microblaze-toolchain from source on a 64 bits linux system, but got stuck. The sou...

2 19yrs

tralalal

2 19yrs tralalal

hydraxc

hi i have a question. is there a xbd file (for edk) for the hydraxc available? and where can i find some documentation...

0 19yrs

u_stadler

0 19yrs u_stadler

Xilinx core generator MIG module generates a slow timing for a DDR2 SDRAM controller

Hello. I've used the Xilinx core generator MIG module to generate a DDR2 SDRAM controller. The design supports generics...

4 19yrs

damicha

4 19yrs damicha

ACM SAC 08: DEADLINE EXTENSION (16 Sept, 2007)

SUBMISSION DEADLINE: September 16th, 2007 SUBMISSION SITE: http://sac.cs.iupui.edu/SAC2008/ CALL FOR PAPERS - SAC 2008...

0 19yrs

ronaldomenezes

0 19yrs ronaldomenezes

Uses of Gray code in digital design

Hello, Most books on digital design discuss Gray codes. However, most of the focus is on generating these codes, rather...

56 19yrs

richard.melikson

56 19yrs richard.melikson

Question about Virtex-4 DCM

I have an application where I need to model a circuit that has two power rails. A Vitrex-4 has only one internal power...

2 19yrs

ghelbig

2 19yrs ghelbig

1/2 Convolutional Encoding of CNAV Data

Does anyone know how to implement a 1/2 (1 binary bit in, 2 out, message length of 7) convolutional encoder in HDL? I a...

0 19yrs

amitpatel130

0 19yrs amitpatel130

What is called carry chain structure in FPGA is called in IC?

Hi, I want to know what is called carry chain structure in FPGA is called in IC? Thank you. Weng

6 19yrs

wtxwtx

6 19yrs wtxwtx

What is the name of Altera latest and most advanced chip serial that is competable in technology with Vertex V in terms of system strucute(LUT6...)

Hi, I would like to know what is the name of Altera latest and most advanced chip serial that is competable in technolo...

2 19yrs

wtxwtx

2 19yrs wtxwtx

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