[Nios II] How fast the cpu in Nios II can reach in the Cycone ?

lexluthor pisze:

No. Take a look over assembler file. It's not a single instruction. Additionaly NIOS need more than one clk cycle for instruction execution ( or maybe not) But anyway you can add hardware extension for special request (like parallel to serial hardware conversion)

Adam

Short answer: no.

Medium answer:

Your code will look roughly like this in pseudo-assembler:

load R1,PIO_0_BASE # target address load R2,0 # data initialization loop: store R2,[R1] incr R2 jump loop

The fast version of NIOS II takes roughly two clock cycles per instruction - a 100MHz clock should give you around 50MIPS best case.

In your loop you will need three instructions per iteration. The code will fit into the single-cycle cache, freeing up the bus.

The PIO implementation uses a single cycle write, so assuming you placed it on the same bus as the processor, this won't be a bottleneck.

So your best-case rate of change on the PIO port is a little under 17MHz.

Kind regards,

Iwo

I've not used it, but I think Altera's C2H can take code similar to that and wrap a custom DMA engine around it automagically. Or so the FAE said!