I need the FIFO36 entity for XAPP851 (DDR SDRAM Controller Using Virtex-5 FPGA Devices). Either it wasn't in the zip file or I lost it while unzipping it.
Thanks in advance,
Brad Smallridge AiVision
I need the FIFO36 entity for XAPP851 (DDR SDRAM Controller Using Virtex-5 FPGA Devices). Either it wasn't in the zip file or I lost it while unzipping it.
Thanks in advance,
Brad Smallridge AiVision
On second look, it cound be that FIFO36 is part of the unisim library? Then why don't I have it? Is it because I'm running ISE 7.1? Or is it that the Web release doesn't support it? Is it part of Synplicity?
Brad Smallridge
That's a primitive, so it should be in the UNISIM library. It's new with the Virtex-5 (Virtex-4 had a FIFO16). So you might neet to update ISE. See if you have a fifo36.v in xilinx/verilog/src/unisims. If not you need to update.
-Kevin
Yeah, but I'm trying to fit this code to a Virtex-4 on an ML402 dev board so maybe I'll change the fifo36 back to fifo16. There are two generics on the fifo36 part that don't appear on the fifo16: DO_REG => 1, EN_SYN => FALSE,
Brad Smallridge AiVision
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