1. Home
  2. Field-Programmable Gate Arrays
  3. Quartus II Web Edition License - SOPC Builder generation?

Quartus II Web Edition License - SOPC Builder generation?

If I have the web edition license, is it still possible to use the SOPC builder?

I'm just trying to build one of the projects in the tutorial...

Thanks, Eric

------------------------ This is the error I get

------------------------

Altera SOPC Builder Version 7.00 Build 33 Copyright (c) 1999-2006 Altera Corporation. All rights reserved.

# 2007.10.13 04:40:11 (*) mk_custom_sdk starting # 2007.10.13 04:40:11 (*) Reading project F:/fpga_stuff/dram_system_sopc/nios_system.ptf. # 2007.10.13 04:40:12 (*) Finding all CPUs # 2007.10.13 04:40:12 (*) Finding all available components # 2007.10.13 04:40:12 (*) Reading F:/fpga_stuff/dram_system_sopc/.sopc_builder/install.ptf # 2007.10.13 04:40:12 (*) Found 67 components # 2007.10.13 04:40:13 (*) Finding all peripherals # 2007.10.13 04:40:13 (*) Finding software components # 2007.10.13 04:40:13 (*) (Legacy SDK Generation Skipped) # 2007.10.13 04:40:13 (*) (All TCL Script Generation Skipped) # 2007.10.13 04:40:13 (*) (No Libraries Built) # 2007.10.13 04:40:13 (*) (Contents Generation Skipped) # 2007.10.13 04:40:13 (*) mk_custom_sdk finishing # 2007.10.13 04:40:13 (*) Starting generation for system: nios_system. .. # 2007.10.13 04:40:15 (*) Running Generator Program for cpu_0 # 2007.10.13 04:40:17 (*) Checking for plaintext license. # 2007.10.13 04:40:17 (*) Plaintext license not found. # 2007.10.13 04:40:17 (*) Checking for encrypted license (non-evaluation). # 2007.10.13 04:40:18 (*) Encrypted license not found. Defaulting to OCP evaluation license (produces a time-limited SOF)

ERROR: In object '' of class e_process: can't access `user_attributes_names' field known fields are: _AUTOLOAD_ACCEPT_ALL _asynchronous_contents _built _clock _contents _creation_history _object_list _order _parent_set _project_set _reset _reset_default _signal_list _vhdl_files _vhdl_fixes _vhdl_variables clock_level comment indent isa_dummy name output_as_muxes_and_registers paragraph reset_level sensitivity_list known pointers are: _parent _project keys: _AUTOLOAD_ACCEPT_ALL _permitted _pointers by the way, this object is a dummy

Error: Generator program for module 'cpu_0' did NOT run successfully. generator cmd was 'c:/altera/70/quartus//bin/perl/bin/perl

-Ic:/altera/70/quartus/sopc_builder/bin

-Ic:/altera/70/quartus/sopc_builder/bin/europa

-Ic:/altera/70/quartus/sopc_builder/bin/perl_lib -I.

-IC:/altera/72/ip/nios2_ip/altera_nios2

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_pio

-IC:/altera/72/ip/nios2_ip/altera_nios_custom_instr_interrupt_vector

-IC:/altera/72/ip/nios2_ip/altera_nios_custom_instruction

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_onchip_memory2

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_onchip_memory

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_mutex

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_burst_adapter

-IC:/altera/72/ip/pci_express_compiler/lib/sopc_builder/altera_avalon_pcie_compiler_adapter

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_cf

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_spi

-IC:/altera/72/ip/pci_compiler/lib/sopc_builder/altera_avalon_pci_compiler

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_user_defined_interface

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_pipeline_bridge

-IC:/altera/72/ip/nios2_ip/altera_nios_dev_board_stratix_2s60_rohs

-IC:/altera/72/ip/nios2_ip/altera_nios_custom_instr_bitswap

-IC:/altera/72/ip/sopc_builder_ip/altera_sopc_builder

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_cfi_flash

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_pll

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_sgdma

-IC:/altera/72/ip/nios2_ip/altera_nios_custom_instr_floating_point

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_epcs_flash_controller

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_adapter_upstream_pipeline

-IC:/altera/72/ip/nios2_ip/altera_nios_dev_kit_stratix_edition_sram

-IC:/altera/72/ip/triple_speed_ethernet/lib/sopc_builder/altera_triple_speed_ethernet

-IC:/altera/72/ip/pci_express_compiler/lib/sopc_builder/altera_avalon_pcie_compiler

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_lan91c111

-IC:/altera/72/ip/nios2_ip/altera_nios_dev_kit_stratix_edition_sram2

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_adapter_downstream_pipeline

-IC:/altera/72/ip/nios2_ip/altera_nios_dev_board_stratix_1s40

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_uart

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_new_sdram_controller

-IC:/altera/72/ip/ddr2_high_perf/lib/sopc_builder/ddr2_high_perf

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_adapter_waitrequest_pipeline

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_adapter_slave_y

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_clock_adapter

-IC:/altera/72/ip/pci_compiler/lib/sopc_builder/altera_avalon_pci_compiler_adapter

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_mailbox

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_asmi

-IC:/altera/72/ip/sopc_builder_ip/amd_avalon_am29lv065d_flash

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_lcd_16207

-IC:/altera/72/ip/nios2_ip/altera_nios_custom_instr_endian_converter

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_jtag_uart

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_adapter_master_y

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_endian_adapter

-IC:/altera/72/ip/nios2_ip/altera_nios_dev_board_cyclone_1c20

-IC:/altera/72/ip/nios2_ip/altera_nios_dev_board_stratix_1s10_es

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_tri_state_bridge

-IC:/altera/72/ip/nios2_ip/altera_nios_dev_board_cyclone_2c35

-IC:/altera/72/ip/sopc_builder_ip/no_legacy_module

-IC:/altera/72/ip/sopc_builder_ip/amd_avalon_am29lv128m_flash

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_cy7c1380_ssram

-IC:/altera/72/ip/nios2_ip/altera_nios2

-IC:/altera/72/ip/ddr_ddr2_sdram/lib/sopc_builder/ddr_sdram_component

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_cs8900

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_performance_counter

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_sysid

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_fifo

-IC:/altera/72/ip/ddr_high_perf/lib/sopc_builder/ddr_high_perf

-IC:/altera/72/ip/nios2_ip/altera_nios_dev_board_stratix_2s60_es

-IC:/altera/72/ip/ddr_ddr2_sdram/lib/sopc_builder/ddr2_sdram_component

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_timer

-IC:/altera/72/ip/ddr3_high_perf/lib/sopc_builder/ddr3_high_perf

-IC:/altera/72/ip/nios2_ip/altera_nios_multiply

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_dma

-IC:/altera/72/ip/nios2_ip/altera_nios_dev_board_stratix_1s10

-IC:/altera/72/ip/sopc_builder_ip/altera_avalon_clock_crossing

-IC:/altera/72/ip/nios2_ip/altera_nios_dev_board_stratix_2s60 C:/altera/72/ip/nios2_ip/altera_nios2/cpu_core_select.pl

--system_name=nios_system --target_module_name=cpu_0

--system_directory=F:/fpga_stuff/dram_system_sopc

--sopc_directory=c:/altera/70/quartus/sopc_builder

--sopc_lib_path=F:/fpga_stuff/dram_system_sopc+C:/altera/72/ip/pci_express_compiler/lib/sopc_builder+C:/altera/72/ip/ddr3_high_perf/lib/sopc_builder+C:/altera/72/ip/ddr2_high_perf/lib/sopc_builder+C:/altera/72/ip/ddr_high_perf/lib/sopc_builder+C:/altera/72/ip/sopc_builder_ip+C:/altera/72/ip/nios2_ip+C:/altera/72/ip/triple_speed_ethernet/lib/sopc_builder+C:/altera/72/ip/pci_compiler/lib/sopc_builder+C:/altera/72/ip/ddr_ddr2_sdram/lib/sopc_builder+c:/altera/70/quartus/sopc_builder/components

--generate=1 --verbose=0 --software_only=0

--module_lib_dir=C:/altera/72/ip/nios2_ip/altera_nios2

--sopc_quartus_dir=c:/altera/70/quartus/ --projectname=dram_system.quartus'

Error in processing. System NOT successfully generated.

Reply to
Eric
Loading thread data ...

--sopc_lib_path=F:/fpga_stuff/dram_system_sopc+C:/altera/72/ip/pci_express_compiler/lib/sopc_builder+C:/altera/72/ip/ddr3_high_perf/lib/sopc_builder+C:/altera/72/ip/ddr2_high_perf/lib/sopc_builder+C:/altera/72/ip/ddr_high_perf/lib/sopc_builder+C:/altera/72/ip/sopc_builder_ip+C:/altera/72/ip/nios2_ip+C:/altera/72/ip/triple_speed_ethernet/lib/sopc_builder+C:/altera/72/ip/pci_compiler/lib/sopc_builder+C:/altera/72/ip/ddr_ddr2_sdram/lib/sopc_builder+c:/altera/70/quartus/sopc_builder/components

(serious snippage above)

You are trying to build with a mixture of 7.0 and 7.2 components.

That will NOT work, web-pack or subscription. At least it never has for me...

G.

Reply to
ghelbig

I thought that might be the problem after I posted so I upgraded to v7.2. I still got errors so I tried a clean install on a different PC. The errors are different this time, but I had thought maybe it was still the license issue so I didn't update. I also tried different builds with different components. All I really need is the SDRAM controller but it says I need the avalon master if that's all I select. So I guess I need the NIOS processor, on-board memory, and SDRAM. With those selected, I get the errors below.

Thanks for your help, Eric

----------------- Info: Info: Elapsed time: 00:00:00 Info: Starting PTF file elaboration. 3 [main] sh 4480 fork: child 4880 - died waiting for longjmp before initialization, errno 11 c:/altera/72/quartus/sopc_builder/bin/nios_sh: fork: Resource temporarily unavailable . . . c:/altera/72/quartus/sopc_builder/bin/nios_sh: fork: Resource temporarily unavailable Error: System generation failed.

Reply to
Eric

You can't build a NIOS system without a NIOS processor; it just won't let you. (The NIOS processor is the default Avalon master.)

The fork call failing could be from just about anything. Two things that come to mind are (1) Running on an unsupported OS, or (2) The web- pack is missing the routine that SOPC is trying to fork to.

I would question the use of an Avalon target outside of a NIOS system. If you don't need to support the Avalon fabric, there are better ways of doing it.

G.

one of two things. There could be more, but

Reply to
ghelbig

You know, both of my systems are running Vista. I'll try to run it off a WinXP system and see how that goes. That may solve it!

What is a better way? I downloaded a SDRAM controller from the Altera site and have been trying to get that to work the last couple of days. I might be close, but looking at what the NIOS system has to offer, it might be a better solution.

To give you a better idea of what I'm doing, I'm trying to run an experiment on the radiation effects on DRAM for my thesis. I didn't pick DRAM, my adviser did, and I think he severely underestimated the challenge it would be for a non-computer engineer. I'm an EE but more on the materials side of things (hence the radiation effects). The device needs to be in operation for the test and I just need to write a simple pattern. I do need to control the refresh rate and read from it though.

Thanks, Eric

Reply to
Eric

Why not start with an fpga demo board already configured with dram, an fpga controller module, and a cpu.

All you would need is an HDL wrapper to cook the refresh.

-- Mike Treseler

Reply to
Mike Treseler

That was it! I installed Quartus II on a friend's computer and it was able to generate it fine.

Thanks for the help! Eric

Reply to
sendthis

That was it! I installed Quartus II on a friend's computer and it was able to generate it fine.

Thanks for the help! Eric

Reply to
sendthis

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.