So I thought I would try out this MIG thing I see mentioned occasionally, But according to
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Software Requirements
- ISE 9.2.01i
- Windows XP (32 bit)
So is MIG really w- MIG is no longer provided as a separate download, but is now incorporated into IP Updates. MIG v1.73 is available through 9.2i IP Update 1.
So does anyone know if older versions of MIG are available somewhere (I have not been able to find them)? Does it run under Wine maybe? Is it worth bothering with (I am specifically interested in a plain DDR interface)?
i had the same problem a couple of weeks before, but in the end i booted my winXP image in VMware generated the core and the used the generated design under linux.
as far as i know you have to have the latest IP upgrade installed, especially for the DDR controller , but MIG only works under winXP!
i would not recommend to try it with wine, cause if its running under wine, you still have to install the hole webpack 9,2, and it needs lots of diskspace.
but anyway i did not get the ddr controller core working, cause the [O| I]DDR entity's used for data capture produced Xs in the calibration process and those Xs propagated throw the hole core! well it was the first time i used to try working with DDR, so it might be an error or some wrong constraints by me.. i found a thread with people having the same problem, but in german:
Well... I don't have WinXP (or Vista for that matter) so that is not an option for me. Okay, technically I guess I paid for them, but I never booted or used them. I am not going to bother with VMware/Windows. I do have Win2000 around that I can boot if absolutely necessary.
Diskspace is cheap and I have plenty of that, so I might give it a try sometime. I found a tool from Xilin called mig007_rel6, which is used for DDR designs on V2P (yes I am using V2P devices, and I know the current "real" MIG does not support them). I guess this is an early incarnation of MIG, though the exact relationship is a bit cryptic. It partially works under Wine, but doesn't generate the output files, and is prone to hangs. But it seems to work under Win2000, so I guess I'll use that for now.
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Well, it has been a long time since I bothered with simulating a back annotated design. I am not sure it is worth the trouble.
I have found the documentation for the design generated by this version of mig to be a bit cryptic, and the generated design/testbench doesn't seem to work as is, at least not in a functional simulation. I think the problem is that without actual LUT/routing delays for the DQS delay lines, the simulation won't work, though I am still checking into that.
And indeed, adding a small bit of delay to the dqs_delay entity does fix the simulation. Since synthesis tools will ignore delays, it is a bit of a mystery why this was not already included, and how the simulation could possibly have worked without it.
My immediate use was for a V2Pro device, so I probably will have to stick to the old tool for that. But I was also looking ahead toward using the V5, and hoping the design doesn't need to change much in the migration.
Just for the sake of completeness, I discovered that in the user interface generated by that tool, some signals are clocked on the system clock, some on a 90 degree phase shifted clock, and some on a 180 degree phase shifted clock. Yikes! So much for an "easy" interface. So I guess I won't be using that.
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