i want to read & write data to/from a fifo placed in fpga. MCU's external bus is connected to the chip. I am using the sync-fifo ip of Altera CycloneII. The data bus and control signal are connected to fifo directly. it's unfortune that when i read once from bus, data would be read twice from fifo because there are two clock rising edges during read signal(low active) is resetted. I think it will read more datas from fifo if the read signal is resetted long enough. Is there any good design for fifo interface connecting on the exteranl bus?
- posted
16 years ago