The spec you reference is the diode clamp, not the driver.
However, you may do what you are suggesting, and not damage the FPGA.
There are many IO standards with currents of up to 60 mA (source/sink), and the device is designed with margin so that these interfaces will run for more then twenty years without a reliability concern.
Although not recommended (and certainly not warrantied), we have seen IOs shorted to ground, or Vcc, and placed in the opposite driving state, and shipped to customers, returned, and tested just fine.
A directly shorted output, when programmed for 24 mA LVCMOS (the strongest standard) will max out at about 120 mA of source current at nominal process/voltage/temperature.
If programmed for less current, then the short circuit current will also be less.
If you want to see what kind of drive current you get, you need to use the IBIS models to simulate your particular circuit, with your IO standard. With IBIS, there is also the FAST/STRONG process/voltage/temperature corner modeled, so you can see what the largest current is likely to be when you get a fast process part, operate at high voltages, and low temperatures.
For example, a 2.5V LVCMOS 12 mA Spartan3 IO driving into a 1 ohm to ground sources ~ 70 mA at the FAST/STRONG IBIS PVT corner (Mentor/HyperLynx with latest IBIS models).