Maximum current drive according to datasheet ?!

I/

It is a very bad idea to operate at "Absolute Maximum Ratings" fo extended periods. These are "NEVER exceed" limits. You should no intentionally exceed the "standard" output current limit (possibly 24mA depending on which output type you set this to be). If you need about a amp of current drive, you will need an external high current driver, suc as an emitter follower.

I don't want actually to drive a load with 100mA;the thing is that I will connect different boards on this board with the FPGA. I want to protect the FPGA output pins from short-circuits to GND, without effecting the maximum datatransfer (100 MHz). The simplest solution I found is connecting a series resistor. The question now is what resistor value should I use. If I used a resistor as high as 150 Ohm (~3.3V/24ma) I might not be able to transfer data rate up to 100 MHz. Yous see what my problem is!

JJ

JJ,

The spec you reference is the diode clamp, not the driver.

However, you may do what you are suggesting, and not damage the FPGA.

There are many IO standards with currents of up to 60 mA (source/sink), and the device is designed with margin so that these interfaces will run for more then twenty years without a reliability concern.

Although not recommended (and certainly not warrantied), we have seen IOs shorted to ground, or Vcc, and placed in the opposite driving state, and shipped to customers, returned, and tested just fine.

A directly shorted output, when programmed for 24 mA LVCMOS (the strongest standard) will max out at about 120 mA of source current at nominal process/voltage/temperature.

If programmed for less current, then the short circuit current will also be less.

If you want to see what kind of drive current you get, you need to use the IBIS models to simulate your particular circuit, with your IO standard. With IBIS, there is also the FAST/STRONG process/voltage/temperature corner modeled, so you can see what the largest current is likely to be when you get a fast process part, operate at high voltages, and low temperatures.

For example, a 2.5V LVCMOS 12 mA Spartan3 IO driving into a 1 ohm to ground sources ~ 70 mA at the FAST/STRONG IBIS PVT corner (Mentor/HyperLynx with latest IBIS models).

Austin

JJ,

You do not need to protect against momentary shorts to ground, or Vcco (as long as you are within our abs max limits -- which you may well be for a LVCMOS 23.5V 12 mA output as mentioned in the previous post).

What will KILL any CMOS part, is a momentary short to a negative voltage, which causes currents in excess of 200 mA to flow (in telecom, with -48 battery everywhere, this is a real concern, as it is instant death to short to -48V!!!!).

Next, Xilinx abs max specs are perhaps different from some of our competition: they are the limits at which there is no damage, or reliability concerns (ie at these extremes, less than 0.1% of the parts will fail after 20 years under these conditions).

Often, manufacturers use the "abs max" as where the damage exceeds the

0.1%/year at end of life, as it looks so much better (it makes their parts appear more robust, when they are not that robust at all -- we all use a standard foundry process, and all use similar design rules, so we all have really the similar behavior when it comes to overstress, reliability and failure).

TANSTAFL

Austin

If you want to spend time protecting your design from short-circuited pins, consider a different approach: make your outputs I/O signals. Monitor the output levels as detected by the inputs. If the signal is truly grounded, a high output drive won't bring the voltage level above threshold under DC drive. A similar argument works for shorts to VCC. While the expected output state and the corresponding input are typicall off by a couple nanoseconds, the signal level should always be established at the next clock for slow clocks and within 2 periods for faster clocks that are expected to establish their level at the receiver within the 1 clock period.

You end up without compromise on your connection speed and can offer a fault monitor to the user. Check with your manufacturer, but the absolute maximums should be for the DC case, not the temporary short for a couple clocks; my understanding is that modern FPGAs can drive those direct shorts for a period of time with no issues - it's the extended drive that can cause severe problems.

- John_H

@Austin

The problem is that the shorts may not be momentary.

@John_H

| | (FPGA) pin A |--------->| pin B (DUT) | | | |

The shorts cases on the Device-under-Test(DUT) are:

1) pin B is shorted to GND 2) pin B is shorted to VCC

If pin B on the DUT is an input pin, and I try to measure the state of that pin, the FPGA will read it unexactly as either high or low, since pin B is floating. If I enabled a pull-up resistor on pin A on the FPGA, I can check if pin B is shorted to GND, but If pin B is shorted to VCC, I wont know if its because of the pull-up resistor on the FPGA pin or because of an error. Please correct me if I am wrong.

So IMHO, an effective solution is a series resistor. But since the fastest signals I will be getting through the FPGA is 100 MHz, I don't know if this is ok or not. I checked the IBIS model, there one can find the rise and fall time with a 50Ohm resistor, but I want the data for 100 Ohm.

JJ

Couple of solutions: Look at universal programmers

They have parallel R (~1K) and small Cap (20-100pF region), so the edges are fast, but a stuck pin causes little grief. That also protects against DC drive outside the rails.

Or you can add drive-check logic inside the FPGA, and read-back to check if the Driven level, is ever Pin level, for some defined time limit. If it is, you remoe the drive, and either flag it, or go into a power-save hiccup mode (see SMPS)

-jg

If your DUT is shorted to ground (pin B) and you only ever drive ground, there's not a problem. If the pin is shorted to VCC and you never drive anything but VCC, there's not a problem. If the pin is shorted to another pin and the two outputs driving those pins are always the same state, there's not a problem.

If you drive an output that doesn't quickly settle to its expected logic state, you have a problem and can tristate that signal and raise a flag with no damage to the FPGA and no compromise on the communication speed or signal fidelity.

Series resistors will also work but will not flag the customer that there's a problem with the DUT.

All that having been said, if your DUT is an unterminated signal with a single load (rather than a daisy-chain of signals) you may do better with 33 ohm to 50 ohm series resistors depending on the board trace impedances. The source termination will drive the signal to about half the expected logic level until the open is detected on the other end of the transmission line. When the reflection from the open reflects back, rather than the current driving back into the output because of a reflected over-voltage, the reflected voltage will be correct and the output simply stop driving. For these terminations, it's often best to be smaller than the characteristic impedance because the drive has an added effective impedance; the combination is what ideally matches the transmission line impedance.

- John_H