Xilinx Parallel Cable IV, API spec

Is the hardware API for "Xilinx Parallel Cable IV Model DLC7" published or does one have to figure that out by traditional engineering methods ..? (I want to know how to talk to the programmer cable by setting bits at port 0x378..)

Reply to
kgll8ss
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Maybe Xilinx Parallel Cable IV is backwards compatible with Paralllel Cable III ..?? which is supported by xilprg-0.5 it seems.

Reply to
kgll8ss

it is SUPER SECRET :(

thats also the reason there are no 3rd party drivers thats the reason why it works so bad - on most cases the Cable IV works in Cable III fallback mode because of SUPERS**** windriver stuff that just failes

the jedec file can however be readback, and i have jedec to vhdl convertert that converts 98% correctly back to vhdl but have had no time to fully RE the protocol

if somebody is interested i can release the jed2vhdl converter with source codes, after little tweaking it should be able to produce VHDL that can be compiled back to working cable IV CPLD

Antti

Reply to
Antti

The Parallel cable IV DLC7 rev4 uses Xilinx XCR3384XL (384 Macrocell CPLD, 5V tolerant I/O pins with 3.3V core supply) and 40.000MHz clock. Which software makes direct use of this cable ..?, trying to figure out a setup for testing. Such that I can trigger an operation and measure the resulting action.

The P-IV advantages over a plain parallel port interface is likely only data integrity and improved speed over plain bit-banging. So it uses ECP to get fast data transfer and add some data integrity check like crc. Uses some fifo that directly feed the fpga through jtag or cclk/d0 interface. In essence: Parallel ECP -> CRC -> FIFO -> Bitbang

Otoh, It seems almost simpler to put together a CPLD + PHY and some cables that will do the job without loops & hoops :), but a finished circuit has some advantages.

Don't forget to bite the hand that buys from you! :-)

Reply to
kgll8ss

I this day and age you might as well use USB, getting you compatability with your travel laptop, etc...

Reply to
cs_posting

However, if you want to write your own code to talk to the standard firmware of the Xilinx Platform USB Cable (rather than using Impact, Chipscope, and XMD), you'll probably *still* have to reverse-engineer the CPLD bits.

Reply to
Eric Smith

yes if you want to talk to ANY currently supported by xilinx cable you need RE :( only cable IV and usb cable are supported since xilinx has officially dropped Cable III support

Antti

Reply to
Antti

But why would you want to use an expensive proprietary cable?

Get a cheap board with the cypress fx2 chip and implement a programmer on that.

If you really want a manufacturer design for some reason, I believe the working of the altera usb blaster has been explained well enough that emulating it in an fx2 is possible. Besides, wouldn't it be fun to program a xilinx part with an (emulated) altera cable?

Reply to
cs_posting

Because I actually *want* to be able to use the Xilinx tools, especially Chipscope Pro.

Reply to
Eric Smith

If you are intending to use the xilinx tools, then why can't you use the xilinx tools to program the parts? ie, why do you need to talk to the cable yourself??

Reply to
cs_posting

REASON 1:

tools provided by xilinx for Cable IV fail on most PC to work in high speed Cable IV mode and fall back to Cable III compatible mode

REASON 2:

xilinx tools are not sufficient for many tasks :( like if you want to program SPI flash on S3E over platform USB cable.. you can not, so need to RE the platform cable todo it, just one example

Antti

Reply to
Antti

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