Field-Programmable Gate Arrays

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How to simulate these example CORDIC code?

Hi, I want to learn the implementation of CORDIC. I find the following website has some code which I would like begin w...
13 comments posted 18yrs
posted by rxjwg98
13 comments posted 18yrs posted by rxjwg98

can't read/load memory contents

Hello there, one of new members around here. I've got a problem while i try to retrieve/pass over some values to memory...
7 comments posted 18yrs
posted by dartanians
7 comments posted 18yrs posted by dartanians

xilinx spartan 3 + 16 adc

Hi I'd like to ask if that device will process data from 16 ADC (20 bit, 44,1kHz) to one output stream (does it depend...
8 comments posted 18yrs
posted by wojjed
8 comments posted 18yrs posted by wojjed

Virtex 5 PCB Designers Guide: required capacitors

Hi all, I've some trouble designing a virtex 5 board. I use the "Xilinx Virtex 5 LX development kit" schematic ( provid...
1 comments posted 18yrs
posted by michel.talon
1 comments posted 18yrs posted by michel.talon

React on falling edge in testbench

Hi, is it possible to make an input react on a falling edge of an output in a vhdl testbench? i'm using modelsim se 6 a...
2 comments posted 18yrs
posted by timo.g
2 comments posted 18yrs posted by timo.g

converter

hi fnds, is there any software that converts 'c' program to a 'vhdl' program??
3 comments posted 18yrs
posted by dilip.manu
3 comments posted 18yrs posted by dilip.manu

PCI Mezzanine Card with Xilinx Virtex-II

Hi I would like to use the following evaluation board to run my implementation: http://www.alpha-data.com/adm-xrc-ii.ht...
5 comments posted 18yrs
posted by Patrick.Bateman23
5 comments posted 18yrs posted by Patrick.Bateman23

DDR2 dqs pin // virtex4

Hi, I just bougth a card with FPGA "Virtex4 XC4VLX60 668pinBGA -11" The board is equiped with a DDR2 SDRAM memorie. FPG...
4 comments posted 18yrs
posted by bhb22l
4 comments posted 18yrs posted by bhb22l

DCM with instable clock

In a design, I have to generate several clocks with precisely phase relationship, I'd like to use DCM. But the clock_in...
11 comments posted 18yrs
posted by wxy0624
11 comments posted 18yrs posted by wxy0624

Unable to scan device chain

I'm soldering up my first FPGA design and I'm getting discouraged. I'm using an Altera Cycline with an EPCS1 serial con...
7 comments posted 18yrs
posted by nevo_n
7 comments posted 18yrs posted by nevo_n

Measuring setup and hold time in Lab

Hi all, How can we measure setup and hold time of a flip-flop on FPGA in lab ? Regards, Ved
9 comments posted 18yrs
posted by vedpsingh
9 comments posted 18yrs posted by vedpsingh

Xilinx XST 8.2, Error on multi-source, bug?

Hi, I'm using Xilinx 8.2.03i and I get an Error Xst:528 "Multi-source in Unit ..." It's a wire in a submodule and i che...
4 comments posted 18yrs
posted by timo.g
4 comments posted 18yrs posted by timo.g

partial dynamic reconfiguration on Virtex-4 SX35

Hi, I have just begin my PhD on SDR and I will have to use a FPGA with partial dynamic reconfiguration. The system whic...
6 comments posted 18yrs
posted by Gael.Abgrall
6 comments posted 18yrs posted by Gael.Abgrall