Field-Programmable Gate Arrays

xilinx spartan 3 + 16 adc

Hi I'd like to ask if that device will process data from 16 ADC (20 bit, 44,1kHz) to one output stream (does it depend...

8 comments posted 18yrs

posted by wojjed

8 comments posted 18yrs posted by wojjed

Registrations open for VLSI Conference 2008 in Hyderabad, India

The '21st International Conference on VLSI Design and the 7th International Conference on Embedded Systems' are being h...

0 comments posted 18yrs

posted by gdbansal

0 comments posted 18yrs posted by gdbansal

Virtex 5 PCB Designers Guide: required capacitors

Hi all, I've some trouble designing a virtex 5 board. I use the "Xilinx Virtex 5 LX development kit" schematic ( provid...

1 comments posted 18yrs

posted by michel.talon

1 comments posted 18yrs posted by michel.talon

React on falling edge in testbench

Hi, is it possible to make an input react on a falling edge of an output in a vhdl testbench? i'm using modelsim se 6 a...

2 comments posted 18yrs

posted by timo.g

2 comments posted 18yrs posted by timo.g

converter

hi fnds, is there any software that converts 'c' program to a 'vhdl' program??

3 comments posted 18yrs

posted by dilip.manu

3 comments posted 18yrs posted by dilip.manu

PCI Mezzanine Card with Xilinx Virtex-II

Hi I would like to use the following evaluation board to run my implementation: http://www.alpha-data.com/adm-xrc-ii.ht...

5 comments posted 18yrs

posted by Patrick.Bateman23

5 comments posted 18yrs posted by Patrick.Bateman23

DDR2 dqs pin // virtex4

Hi, I just bougth a card with FPGA "Virtex4 XC4VLX60 668pinBGA -11" The board is equiped with a DDR2 SDRAM memorie. FPG...

4 comments posted 18yrs

posted by bhb22l

4 comments posted 18yrs posted by bhb22l

DCM with instable clock

In a design, I have to generate several clocks with precisely phase relationship, I'd like to use DCM. But the clock_in...

11 comments posted 18yrs

posted by wxy0624

11 comments posted 18yrs posted by wxy0624

Unable to scan device chain

I'm soldering up my first FPGA design and I'm getting discouraged. I'm using an Altera Cycline with an EPCS1 serial con...

7 comments posted 18yrs

posted by nevo_n

7 comments posted 18yrs posted by nevo_n

EDK + Modelsim simulation : Memory allocation failure

Dear When I simulate one EDK project (with multi-processors), Modelsim reports an error "Memory allocation failure". I...

4 comments posted 18yrs

posted by pasacco

4 comments posted 18yrs posted by pasacco

Measuring setup and hold time in Lab

Hi all, How can we measure setup and hold time of a flip-flop on FPGA in lab ? Regards, Ved

9 comments posted 18yrs

posted by vedpsingh

9 comments posted 18yrs posted by vedpsingh

Xilinx XST 8.2, Error on multi-source, bug?

Hi, I'm using Xilinx 8.2.03i and I get an Error Xst:528 "Multi-source in Unit ..." It's a wire in a submodule and i che...

4 comments posted 18yrs

posted by timo.g

4 comments posted 18yrs posted by timo.g

partial dynamic reconfiguration on Virtex-4 SX35

Hi, I have just begin my PhD on SDR and I will have to use a FPGA with partial dynamic reconfiguration. The system whic...

6 comments posted 18yrs

posted by Gael.Abgrall

6 comments posted 18yrs posted by Gael.Abgrall

An error occured while using Dual Port Block Memory

Hi! I am using Dual Port Block Memory in Virtex-II, V8.2. During simulation in Modelsim, i have encountered an error th...

2 comments posted 18yrs

posted by spygame81

2 comments posted 18yrs posted by spygame81

FPGA Editor (9.2.03i) under Linux x86_64

I am not able to run the fpga_editor (64-bit ISE install) under my Fedora 7, x86_64 system. After I set the DISPLAY var...

8 comments posted 18yrs

posted by no

8 comments posted 18yrs posted by no