xilinx spartan 3 + 16 adc

Could you be more specific? What kind of ADC? What kind of spartan3? What exactly do you want to do?

Regards,

Jerzy Gbur

sorry i did miss "xc3s50" i want to connect 16 outputs from ADC (dont know specification yet) to FPGA inputs and convert them to one stream.

regards

the 44.1 khz is a serial output rate of the ADC? and the total output rate without headers, dataprocessing or whatever is 44.1*20*16= 14 Mbps? Should be possible with such a device if you choose a correct clock frequency. Taco

I am sure the OP is talking about audio ADCs, so 44.1 kHz is not serial rate but rather parallel. However, your calculation of the total bandwidth required is still correct... Obviously this speed is not an issue with any of the modern FPGAs.

/Mikhail

The issue will be the number of parallel inputs to the FPGA.

? I'm not sure I have ever seen a 20+ bit 44Khz samplig ADC with a parallel data stream ? Most use a SSI serial interface (which is where the 14 Mbps numbers are coming from ) So, depending on what the OP means exactly by "process data", this looks doable in a FPGA.

-jg

Can't recall any offhand. It was common enough in the 16 bit days though. There may have been 20-bit offerings from some of the hybrid manufacturers, Analogic maybe?

- Brian

Sure the output of the ADC is most likely serial. I was just trying to say that the 44.1 kHz is not the data output serial clock, but rather the output sampling clock frequency.

/Mikhail