Latest threads in Field-Programmable Gate Arrays

System Generator Design examples for spartan3, virtex 2pro?

Can someone please point to a site where we can get some good design examples for Sysgen (not the ones mentioned in the...

0 18yrs

kksingh.sdr

0 18yrs kksingh.sdr

Getting started guide for Digilent Spartan 3E Starter Board?

Hi there - I recently got a Digilent Spartan 3E Starter Board (http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EB...

6 18yrs

nleahcim

6 18yrs nleahcim

Spartan-3E starter kit, what's "J8" 6-pin for?

What's the 6-pin connection "J8" on the lower-left of the Xilinx/ Digilent "Spartan-3E starter kit" (rev D) wired too ....

4 18yrs

posedge52

4 18yrs posedge52

Using LVDS_25 with 3.3V Vcco.

What voltage swing will and common voltage will a LVDS_25 configured port output when the Vcco is 3.3V and not 2.5V as t...

9 18yrs

posedge52

9 18yrs posedge52

serial ATA question

This is probably a long shot but I'm wondering if serial ATA can be run at a speed less than 1.5 Gbps? I have a V4 fpga...

3 18yrs

cepope

3 18yrs cepope

Connecting BRAM block to Self designed BRAM controller

Hi all, I am using XPS 8.2i and ISE 8.2i and a virtex-4 board.As a part of assignment, I have to write a verilog/vhdl c...

0 18yrs

rinky.singh.86

0 18yrs rinky.singh.86

Chrontel 7010A

Does anybody have experience with Chrontel 7010A (CH7010A)? I input BT.656 digital video to Chrontel 7010A. I'm trying...

1 18yrs

ckaleli

1 18yrs ckaleli

using fstream to access File on Compact Flash Card

Specification EDK version:8.2i FPGA Board: Virtex II Pro Compiler : mb-g++ I'm tring to create a file stream using ifst...

1 18yrs

priyanthads

1 18yrs priyanthads

xilinx v5 configeration problem

When i use chipscope 9.2 to configerate bit file, sometimes will occour warning like this "WARNING - Device 0: ICON Cor...

3 18yrs

mynewlifever

3 18yrs mynewlifever

Spartan 3E starter kit expansion boards - Gb ethernet & video

I have been thinking about doing 1 or 2 expansion boards for the Spartan 3E starter board to add Gb ethernet & camera c...

0 18yrs

rats

0 18yrs rats

`ifdef XST?

Does anybody know if XST defines any testable variables when compiling verilog code? Some of the compilers or simulator...

1 18yrs

neil.steiner

1 18yrs neil.steiner

Darnaw1 User Manual

First cut of the Darnaw1 user manual is now available here http://www.enterpoint.co.uk/moelbryn/Darnaw1_User_Manual_Issu...

0 18yrs

g1

0 18yrs g1

ML505 board Compact Flash

HI everyone, I have purchased ML505 virtex5 based kit for PCIe testing. It has one pre-loaded compact flash with some i...

4 18yrs

sachin.gorkhe

4 18yrs sachin.gorkhe

How do you initialize Xilinx ISOCM memory using DCR interface

I'm trying to use the Xilinx ISOCM memory in a Virtex-II Pro. I can't seem to get it to actually write to the ISOCM BRA...

5 18yrs

hand

5 18yrs hand

WARNING:PAR:289 and bitgen error.

Hello, I'm having problems with XIlinx ISE 9.1. My design works fine on behavioral simulation but when I want to implem...

2 18yrs

dteira

2 18yrs dteira

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