Field-Programmable Gate Arrays

Spartan-3E starter kit, what's "J8" 6-pin for?

What's the 6-pin connection "J8" on the lower-left of the Xilinx/ Digilent "Spartan-3E starter kit" (rev D) wired too ....

4 comments posted 18yrs

posted by posedge52

4 comments posted 18yrs posted by posedge52

Using LVDS_25 with 3.3V Vcco.

What voltage swing will and common voltage will a LVDS_25 configured port output when the Vcco is 3.3V and not 2.5V as t...

9 comments posted 18yrs

posted by posedge52

9 comments posted 18yrs posted by posedge52

serial ATA question

This is probably a long shot but I'm wondering if serial ATA can be run at a speed less than 1.5 Gbps? I have a V4 fpga...

3 comments posted 18yrs

posted by cepope

3 comments posted 18yrs posted by cepope

Connecting BRAM block to Self designed BRAM controller

Hi all, I am using XPS 8.2i and ISE 8.2i and a virtex-4 board.As a part of assignment, I have to write a verilog/vhdl c...

0 comments posted 18yrs

posted by rinky.singh.86

0 comments posted 18yrs posted by rinky.singh.86

Chrontel 7010A

Does anybody have experience with Chrontel 7010A (CH7010A)? I input BT.656 digital video to Chrontel 7010A. I'm trying...

1 comments posted 18yrs

posted by ckaleli

1 comments posted 18yrs posted by ckaleli

using fstream to access File on Compact Flash Card

Specification EDK version:8.2i FPGA Board: Virtex II Pro Compiler : mb-g++ I'm tring to create a file stream using ifst...

1 comments posted 18yrs

posted by priyanthads

1 comments posted 18yrs posted by priyanthads

xilinx v5 configeration problem

When i use chipscope 9.2 to configerate bit file, sometimes will occour warning like this "WARNING - Device 0: ICON Cor...

3 comments posted 18yrs

posted by mynewlifever

3 comments posted 18yrs posted by mynewlifever

Spartan 3E starter kit expansion boards - Gb ethernet & video

I have been thinking about doing 1 or 2 expansion boards for the Spartan 3E starter board to add Gb ethernet & camera c...

0 comments posted 18yrs

posted by rats

0 comments posted 18yrs posted by rats

`ifdef XST?

Does anybody know if XST defines any testable variables when compiling verilog code? Some of the compilers or simulator...

1 comments posted 18yrs

posted by neil.steiner

1 comments posted 18yrs posted by neil.steiner

Darnaw1 User Manual

First cut of the Darnaw1 user manual is now available here http://www.enterpoint.co.uk/moelbryn/Darnaw1_User_Manual_Issu...

0 comments posted 18yrs

posted by g1

0 comments posted 18yrs posted by g1

ML505 board Compact Flash

HI everyone, I have purchased ML505 virtex5 based kit for PCIe testing. It has one pre-loaded compact flash with some i...

4 comments posted 18yrs

posted by sachin.gorkhe

4 comments posted 18yrs posted by sachin.gorkhe

How do you initialize Xilinx ISOCM memory using DCR interface

I'm trying to use the Xilinx ISOCM memory in a Virtex-II Pro. I can't seem to get it to actually write to the ISOCM BRA...

5 comments posted 18yrs

posted by hand

5 comments posted 18yrs posted by hand

WARNING:PAR:289 and bitgen error.

Hello, I'm having problems with XIlinx ISE 9.1. My design works fine on behavioral simulation but when I want to implem...

2 comments posted 18yrs

posted by dteira

2 comments posted 18yrs posted by dteira

VHDL code for component labeling

Hi, I am a bit new to VHDL. Can some one please point me to component labeling (image processing) code in VHDL if there...

1 comments posted 18yrs

posted by sun.radha

1 comments posted 18yrs posted by sun.radha

spartan 3e VQ100 serious question

How come in the pdf of the vq100 diagram, it shows something with 64 pins. This is odd because the spartan 3e sure does...

10 comments posted 18yrs

posted by Josh.OuterSpace

10 comments posted 18yrs posted by Josh.OuterSpace