Xilinx MAC experience ?

Question

Hi all,We are going to start a project in which we will need to use the hardware MAC Ethernet module in a Virtex 5 for high speed transferrs (around 400KB/s) through 1000BT. I'm looking for experience feedbacks : Anyone who has used tihs module without a third-party TCP/IP stack (as we have in mind to generate static size UDP frames directly from the logic due to the high throughput we need, may be with the help of a microblaze for configuration of addresses etc) ? Difficulties ? Quality of the documentation ? Virtex 4 vs 5 ? Reference designs or good sources of information ?Many thanks,Yours,Robert

Robert Lacoste · Accepted Answer

Of course I'm talking of 400Mb/s and not KB..."Robert Lacoste"  a écrit dans le message de news: 476627e9$0$863$

Teo · Answer

Hi,take a look at the GSRD reference design from Xilinx. It uses theTreck TCP/IP stack. Of course you have to evaluate its cost related toyour project, but with the GSRD I can obtain more than 700Mbit/s onTCP.Matteo

John Aderseen · Answer

Hello Rob,Interesting question. From my experience, even if people from Xilinx will tend to make you think that it is not all that complicated (take a look at the GSRD design indeed - it mixes PPC405 - multiport sdram controller amongst others !) if you are not well experienced in VHDL programming for Xilinx components , I wouldn't go there. You will most probably get it up and running however at those transfer rates, things start getting very touchy and you may end up spending lots and lots of time on those little details that make all the difference !Let us know how it turns out !Regards,John"Robert Lacoste"  a écrit dans lemessage de news: 476627e9$0$863$

Ben Jackson · Answer

We generated data by writing directly to a V4 hard_temac. We didn't configure it manually, though, there was other passthrough traffic from a plb_temac. The Linux driver configured the MAC (but there aren't that many host bus registers to set if you want to use only hard_temac). Remember you need a valid header, and an OS network stack is doing a lot behind the scenes to handle routing, arping, etc. If this is going off- board, you will need something to configure your PHY, too.

It's actually easy to inject data into a hard_temac that's also being driven by a plb_temac because the interface lets the hard_temac (or your wedge) flow control the upstream. So you can block the plb_temac (as if you were a slow interface, or experiencing collisions) while you drive the hard_temac with your data.

There are appnotes covering all of it. If you avoid 10/100 (and go 1000 only) things are simpler (MII vs GMII reverses some of the clock flow).

Robert Lacoste · Answer

Many thanks Ben, and all others,  for these feedbacks !Robert"Ben Jackson"  a écrit dans le message de news:

Xilinx MAC experience ?

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