Field-Programmable Gate Arrays

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question on AND

I have 2 inputs x : unsigned bw : integer when x>bw I want to check if x(x'length downto bw) = "1111111......" How do i...
8 comments posted 18yrs
posted by FPGA.unknown
8 comments posted 18yrs posted by FPGA.unknown

XPS MPMC

Hi all , I have been stumped by xilinx tools again ! I have just baught a Evaluation board , whos supporting software ,...
3 comments posted 18yrs
posted by niladri1979
3 comments posted 18yrs posted by niladri1979

Vendors of FPGA's

If I am looking for buying just the FPGA chip itself - not a development board - where could I buy this? What do commerc...
4 comments posted 18yrs
posted by honninghuset
4 comments posted 18yrs posted by honninghuset

What does this do ?

Hi, Can anyone tell me what this bit of code is doing ? -- declarations -----------------------------------------------...
2 comments posted 18yrs
posted by iqbalmuh
2 comments posted 18yrs posted by iqbalmuh

simulation problems

I havw writtent the following code. It compiles correctly. When i run the simulation it just stops and points to this s...
5 comments posted 18yrs
posted by FPGA.unknown
5 comments posted 18yrs posted by FPGA.unknown

Ethernet on recent FPGAs

Hi, Am far from being an expert in fpga usage and programming, I was wondering if there exists any ip cores out there t...
24 comments posted 18yrs
posted by Pat
24 comments posted 18yrs posted by Pat

Differential output drive-strength in spartan-3

I am instantiating an LVPECL iobuffer in a xilinx spartan-3 device. This buffer is sending out data at 150Mbps into an...
6 comments posted 18yrs
posted by jonpry
6 comments posted 18yrs posted by jonpry

Area group constraint

Hi, I have a question regarding area group constraints for Xilinx ISE software Using VHDL to describe this: I have an e...
0 comments posted 18yrs
posted by axr0284
0 comments posted 18yrs posted by axr0284

Camera connection on XUPV2P

Hello, I've some issues hooking up some external components (camera link base cameras) to my XUPV2P board. I've built a...
12 comments posted 18yrs
posted by mjp500
12 comments posted 18yrs posted by mjp500

WebPack on GNU/Linux

Hi all ! I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with iverilog and testbench associated. Wave...
16 comments posted 18yrs
posted by habib
16 comments posted 18yrs posted by habib

round,fix and floor algortihms

I would like to know which round,fix and floor algorithm would be best to be implemented on an FPGA. I am working on a...
13 comments posted 18yrs
posted by FPGA23
13 comments posted 18yrs posted by FPGA23

OpenCores tracker and forum doesn't work?

Hi All, I just tried to submit a bug to OpenCores, and found that even though the report input form works (eg. http://w...
1 comments posted 18yrs
posted by wzab01
1 comments posted 18yrs posted by wzab01

Looking for used spartan3 fpga board

Hi All, I am looking for an old Spartan3a fpga board to test a school project for my sister. If you have and want to sel...
0 comments posted 18yrs
posted by thuyp
0 comments posted 18yrs posted by thuyp

spartan 3e JTAG programming

Hi guys I have two spartan 3e's and a coolrunner in a single JTAG chain. If I program either FPGA from power up its out...
1 comments posted 18yrs
posted by weston_katherine
1 comments posted 18yrs posted by weston_katherine