Hi, I have a question regarding area group constraints for Xilinx ISE software
Using VHDL to describe this: I have an entity A that uses 3 components B, C and D as well as glue logic connecting everything together.
If I set my area constraint as follows: AREA_GROUP "AG_A" RANGE = SLICE_X0Y149:SLICE_X3Y66 ; INST "A" AREA_GROUP = "AG_A";
Will PAR place the entity as well as the components inside the area constraints OR will it map the entity glue logic to the area constraint and then place B, C and D anywhere.
What if I do this: AREA_GROUP "AG_ABCD" RANGE = SLICE_X0Y149:SLICE_X3Y66 ; INST "A" AREA_GROUP = "AG_ABCD"; INST "B" AREA_GROUP = "AG_ABCD"; INST "C" AREA_GROUP = "AG_ABCD"; INST "D" AREA_GROUP = "AG_ABCD";
How different will be the placed design. Thanks for the insight. Amish