WebPack on GNU/Linux

Did it give you any specific errors ? (click on 'Errors' tab at the bottom).

You're doing two assignments to 'out' in the same clock cycle.

Try:

always @(posedge clk) begin if (reset==1) out[7:0]

Le Thu, 03 Jan 2008 15:02:31 +0100, Arlet Ottens a écrit:

No. But i have WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology. (In Warnings TAB)

That's right but i'm not sur that this is an issue in that case. I'm learning Verilog at the moment. Thanks.

I tried this counter module in ISE Webpack 9.2 in Linux, and it builds fine.

The test bench contains constructs that aren't synthesizable, such as the delays, $display() calls, and the fact that it doesn't have any I/O signals.

Le Thu, 03 Jan 2008 15:31:26 +0100, Arlet Ottens a écrit:

waouh ! Is it a GNU/Linux ditrib pb ? I'm running debian GNU/Linux.

That's right. the test bench is here only for getting readeable results with iverilog(or cver) and gtkwave

Many thanks Arlet !

Le Thu, 03 Jan 2008 15:31:26 +0100, Arlet Ottens a écrit:

The problem was that some files in ../bin/lin/ have not executing perms. i made this : chmod +x winds* or something ... and it compiles fine now !

Many thank !

yeah, I get those warnings all the time too.

Ubuntu (Edgy), so it's debian based. I had to install the open motif libs, but that's it.

What device are you targetting ?

Le Thu, 03 Jan 2008 15:45:58 +0100, Arlet Ottens a écrit:

bottom).

Open motif ?? I have download this morning the huge file (1.7G) from Xilinx and just type ./setup as the promise and do weird thing as download ServicePack or something and ... finally it works (almost ... see my post)

Oh just CPLD's for the moment 'cause i'm trying to speak Verilog as well i speak C/C++.

Habib Bouaziz-Viallet wrote: ...

Please edit your quote to keep it readable

-- Uwe Bonnes snipped-for-privacy@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt

--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Doing more than one assignment to a signal is allowed for synthesizable code, both in Verilog and VHDL. The last assignment in the process block takes precedence. (This assumes that all assignments are done in the same process, if not you will have a whole bunch of problems...)

It can allow for quite a bit more readable code in some cases, especially if you have a combinational block where you must be sure to always assign a value to a certain signal in order to avoid a latch.

/Andreas

I didn't know that.. Thanks.

I noticed it synthesized OK, but I assumed the behavior would be unspecified.

Le Fri, 04 Jan 2008 11:51:56 +0100, Arlet Ottens a écrit:

Hey what makes you think that the behaviour would be unspecified ?

That's just what I had assumed. It is actually specified to take the last one, like Andreas said, so your original code works as intended.

Still, you may prefer to make the priority encoding explicit by putting the "out

Glad you found the problem this time; but a pointer to finding problems in general may be useful...

the "Translate" phase is basically the NGDbuild program, which writes a ".bld" report file. This ought to contain a messsage (in your case, such as " was not found, or not executable : NGDbuild aborting".) pointing straight at the problem.

Ditto failures at the "Map" phase; in the ".mrp" map report file, or at the "PAR" phase, in the ".par" report file.

- Brian

I'm not the original guy, nor do I think it's unspecified, but it's not a strange way to interpret a bunch of nonblocking assignments. After all,

Le Fri, 04 Jan 2008 14:25:01 +0000, Brian Drummond a écrit:

Yes it is, but this may be not a general problem because no one has experienced the same.

In fact, be sure that no message of any type has been found in console tab within ise. I've resolved the problem by doing "strace ../bin/lin/ise"

Le Fri, 04 Jan 2008 13:03:59 +0100, Arlet Ottens a écrit: