Field-Programmable Gate Arrays

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Timing Constraint not met

Hi I put a timing constraint in the UCF File where i asked for a minimum frequency of 35 MHz (29 ns) but unfortuatenly...
5 comments posted 18yrs
posted by Clemi_12
5 comments posted 18yrs posted by Clemi_12

Problem in assignment of pins in PACE

Hi all, I have recently just generated HDL netlist from System Generator 9.1 and I have began assigning the pins in PAC...
0 comments posted 18yrs
posted by hilo_pupu
0 comments posted 18yrs posted by hilo_pupu

Strange "Style guide" requirements...

I've been working as a 'consultant' / sub contract engineer with a strong emphasis on FPGA work for about eight years n...
11 comments posted 18yrs
posted by nial*REMOVE_THIS*
11 comments posted 18yrs posted by nial*REMOVE_THIS*

Looking for a development board

Hi everybody , I am looking for a development board. My intention is to devolp a DSP application so ideally should conta...
8 comments posted 18yrs
posted by Alfredo.Taddei
8 comments posted 18yrs posted by Alfredo.Taddei

impact bug or wrong interpretation of xsvf layout?

Hi, While debugging my xsvf parser for ft2232 jtag programmers I experience some really odd behavior; if I swapped my b...
6 comments posted 18yrs
posted by mickeymeeuw
6 comments posted 18yrs posted by mickeymeeuw

Weired Distributed Memory behaviour

Hi As mentioned in an earlier post, I need an asynchonous instead of a synchronous data memory. The design was working...
4 comments posted 18yrs
posted by Gerry
4 comments posted 18yrs posted by Gerry

I/O mode to use for USB ..?

Which I/O mode like LVDS_25 etc.. is suitable to interface USB on a Spartan-3 FPGA ..? (I know the single ended signalin...
7 comments posted 18yrs
posted by Sky465nm
7 comments posted 18yrs posted by Sky465nm

Prom alternatives for xilinx

We are want to use a spartan 3E in the very small chip scale package because of space constraints. However the 4 MBit s...
5 comments posted 18yrs
posted by tralalal
5 comments posted 18yrs posted by tralalal

ML410 and documentation on ALi M1535D+

Hi everybody I had the intention to buy an ML410 board but the local Xilinx reseller told me that there is a problem co...
2 comments posted 18yrs
posted by taileb.mehdi
2 comments posted 18yrs posted by taileb.mehdi

Shutdown parts of core logic on FPGA

Hi NG. I would like to know if it would be possible to shutdown (cut the power) from some parts of the core logic on an...
1 comments posted 18yrs
posted by rgrworking
1 comments posted 18yrs posted by rgrworking

beleive

I can hardly beleive, that when a single FPGA may cost up to 2000$, there is no space for a few hundred kilo- maybe meg...
6 comments posted 18yrs
posted by fbv999
6 comments posted 18yrs posted by fbv999

function/process to generate sine and cosine wave

I would like some guidline on writing a function or process to generate a sine wave and cosine wave. I want to include...
15 comments posted 18yrs
posted by FPGA.unknown
15 comments posted 18yrs posted by FPGA.unknown