Latest threads in Field-Programmable Gate Arrays

Interrupt Handler page missing in from software platform settings in XPS 9.2i

I am trying to port an application from ISE/EDK 8.1i to 9.2i. Everything is going well except for one thing - the page...

1 18yrs

jshamlet

1 18yrs jshamlet

Post PAR simulation is successful but still fails on the board

Hi, I am using a Virtex II development board and am doing some work with a little system on a chip. I am using onboard...

1 18yrs

longbrmb

1 18yrs longbrmb

From ASIC RTL to FPGA, what are the things I should take care of?

I have a project to prototype an ASIC design on FPGA. What are the things I should do? Here is some of my concerns: 1)...

4 18yrs

junsong.liao

4 18yrs junsong.liao

scanf problem in EDk 9.1i (Microbaze)

Hi, How to read an integer from hyperterminal onto a microbaze using EDK 9.1i. Im trying it using scanf but its giving...

6 18yrs

mahesh1280

6 18yrs mahesh1280

Virtex5 BUFR min frequency

Hi all, I've a question about BUFR primitives. I read in the datasheet that BUFR can distribute their output clock on c...

1 18yrs

michel.talon

1 18yrs michel.talon

Which Linux Distro to use for Xilinx tools

Hi, I Love Linux, but currently i have to boot in XP because of xilinx toolset (ISE, EDK, sysgen Matlab, chipscope etc)...

14 18yrs

narendra.sisodiya

14 18yrs narendra.sisodiya

FPGA Programming solution

Greetings , I am trying to implement a solution for an FPGA that needs to be configured with two different programs bec...

30 18yrs

Alfredo.Taddei

30 18yrs Alfredo.Taddei

MIG and Spartan3 for a 112 bit DQ bus (7chips x16)

Hello, Has anybody tried to use MIG with a Spartan 3 to generate a memory controller that has a big DQ bus? I would lik...

1 18yrs

Karel.Deprez

1 18yrs Karel.Deprez

Efficient division algorithm?

I'm going to talk to a potential new client about using FPGAs to accelerate part of their system. As part of what needs...

20 18yrs

nial*REMOVE_THIS*

20 18yrs nial*REMOVE_THIS*

Using Lattice ispLEVER with VHDL libraries

I am trying to pick up the Lattice ispLEVER tool and am having a bit of trouble with it in regards to libraries. I have...

11 18yrs

gnuarm

11 18yrs gnuarm

TCL testcase in Modelsim.

Hello, Does anybody have experience on writing TCL testcase in Modelsim? I only have VHDL simulation license of Modelsi...

6 18yrs

bigyellow

6 18yrs bigyellow

V4FX100 PowerPC PLB issues (and EDK 9.2)

Anyone ever run into an issue where the PowerPC can write to entities on its DPLB, but cannot read from them? I've adde...

3 18yrs

morphiend

3 18yrs morphiend

Define the primary clock with XST in VHDL

Hello Guys, How to specify with XST that an input of a VHDL entity is a clock ? I guess it is not automatic because aft...

2 18yrs

lochen

2 18yrs lochen

MicroBlaze simulator, software ownership rights for SALE

Hi I am making a time limited offer for full ownership rights sale for "XSIM Xilinx Platform Simulator" The simulator w...

3 18yrs

Antti.Lukats

3 18yrs Antti.Lukats

Interface on board ADC to Spartan 3E startkit

Hi, I want to interface on board ADC to spartan 3E startkit. Actually I am developing digital filter in FPGA for that I...

15 18yrs

krunal.coep

15 18yrs krunal.coep