Field-Programmable Gate Arrays

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ADPCM IP Core

Hi, For one of my projects, I am looking for ADPCM IP core. I found a previous thread and a Xilinx release note which s...
0 comments posted 18yrs
posted by togoli
0 comments posted 18yrs posted by togoli

V4FX: LVCMOS25 vs LVCMOS33 output buffer

Hi all, Is there a difference which one is instantiated when the actual VCC in the bank is 3.0V? Thanks, /Mikhail
9 comments posted 18yrs
posted by mbmsv
9 comments posted 18yrs posted by mbmsv

scanf problem in EDk 9.1i (Microbaze)

Hi, How to read an integer from hyperterminal onto a microbaze using EDK 9.1i. Im trying it using scanf but its giving...
6 comments posted 18yrs
posted by mahesh1280
6 comments posted 18yrs posted by mahesh1280

Virtex5 BUFR min frequency

Hi all, I've a question about BUFR primitives. I read in the datasheet that BUFR can distribute their output clock on c...
1 comments posted 18yrs
posted by michel.talon
1 comments posted 18yrs posted by michel.talon

Which Linux Distro to use for Xilinx tools

Hi, I Love Linux, but currently i have to boot in XP because of xilinx toolset (ISE, EDK, sysgen Matlab, chipscope etc)...
14 comments posted 18yrs
posted by narendra.sisodiya
14 comments posted 18yrs posted by narendra.sisodiya

FPGA Programming solution

Greetings , I am trying to implement a solution for an FPGA that needs to be configured with two different programs bec...
30 comments posted 18yrs
posted by Alfredo.Taddei
30 comments posted 18yrs posted by Alfredo.Taddei

MIG and Spartan3 for a 112 bit DQ bus (7chips x16)

Hello, Has anybody tried to use MIG with a Spartan 3 to generate a memory controller that has a big DQ bus? I would lik...
1 comments posted 18yrs
posted by Karel.Deprez
1 comments posted 18yrs posted by Karel.Deprez

Efficient division algorithm?

I'm going to talk to a potential new client about using FPGAs to accelerate part of their system. As part of what needs...
20 comments posted 18yrs
posted by nial*REMOVE_THIS*
20 comments posted 18yrs posted by nial*REMOVE_THIS*

Using Lattice ispLEVER with VHDL libraries

I am trying to pick up the Lattice ispLEVER tool and am having a bit of trouble with it in regards to libraries. I have...
11 comments posted 18yrs
posted by gnuarm
11 comments posted 18yrs posted by gnuarm

TCL testcase in Modelsim.

Hello, Does anybody have experience on writing TCL testcase in Modelsim? I only have VHDL simulation license of Modelsi...
6 comments posted 18yrs
posted by bigyellow
6 comments posted 18yrs posted by bigyellow

V4FX100 PowerPC PLB issues (and EDK 9.2)

Anyone ever run into an issue where the PowerPC can write to entities on its DPLB, but cannot read from them? I've adde...
3 comments posted 18yrs
posted by morphiend
3 comments posted 18yrs posted by morphiend

Define the primary clock with XST in VHDL

Hello Guys, How to specify with XST that an input of a VHDL entity is a clock ? I guess it is not automatic because aft...
2 comments posted 18yrs
posted by lochen
2 comments posted 18yrs posted by lochen