Interview questions

Clemens Blank schrieb:

and the best one I came across was to double the clock frequency. How on earth should this be possible, must be a trap!

For the question about dividing the frequency by two, be sure to note that you wouldn't use the resulting output as a (gated) clock!

To double a frequency the best method is to use a PLL, but this requires some analog components. A DLL works well, but is jittery. A simple dirty method requires just an XOR and a delay element, but that's not a good synchronous design practice.

-Kevin

Having a state machine with three high states followed by 3 low states is a divide by 6, not a divide by 3!

The trick here to getting a 50% duty cycle output is to know that you need the positive edge of the incoming clock to control the rising edge of the output clock and the negative edge to control the falling (or vice-versa). This assumes, of course, that the input clock is

Since most registers can't toggle on both posedge clk and negedge clock in the same flop, the output has to be a combinatorial result from the two edge domains.

- John_H

e.

About clock divider

I ran a series of posts on this:

I also have in my blog a full section on interview questions and puzzles:

hope this helps.

Nir

Depends upon what your criteria of superior is.

Cheers, Jon

An easy answer is to use a DCM in Virtex FPGA ... :-) haha details, as said, PLL and DLL...

Another interesting question I read from a newspaper yesterday, how to get more than 10% gain if share prices increase by 10%?

The best answer to all these questions is a question. Starting with the architecture / type of logic.

Is it?

Leverage.... The same way a 10% drop can cost you much more than 10%!!!

Ofcourse. Interview questions are designed to start a technical debate in order to reveal the applicant's knowledge (or lack thereof).

Is that the only purpose?

What other purpose could there be?

I think you all need the philosophy group. This is the place to come when you have a question that needs an answer, not when you have an urge to consider the meaning of life.

What are you suggesting?

Isn't it obvious?

Last time I looked, a Toggle flip-flop with its output inverted to its input will stop toggling as soon as the output goes high... I think you meant to make a Toggle flip flop using a D flip-flop with the inverted output tied to the D input.

You could do that, but it would be tough to synthesize. A lot easier to have only elements switching on one clock edge or the other. By the way, even so you only get 50% duty cycle out if the clock had 50% duty cycle coming in. There was a nice tool posted called:

Topweaver Anydivider 1.0 Topweaver Tools Family Copyright (c) 2002-2006, Topweaver Author: Song Tianning Website:

Superior for doing what? Resetting sooner whether the clock is running or not? Resetting in a way that doesn't create glitches on the outputs?

Good Luck, Gabor

To whom?