Hi, All!
Need more info about system generator hardware co-simulation interface. Using JTAG for custom board very simply but extremely slow.
How to support hardware co-simulation on custom FPGA boards with high speed interfaces: Ethernet, PCI, USB.
For example:
ML506 board Ethernet co-simulation files, from system generator plugins folder:
eth_cosim_bitgen.opt eth_cosim_core.lna eth_cosim_core_synopsis eth_cosim_impl.opt eth_cosim_top.bmm eth_cosim_top.ucf ML506_PPEth_NonMmPorts.m ML506_PPEth_PostGeneration.m ML506_PPEth_Target.m xltarget.m
How to build such plugin for custom Virtex board?