Design complexity in Logic cells - Virtex-5 FPGA

Mar 12, 2008 5 Replies

Hi, Some IP vendors gives the complexity of the device in terms of "LCs (Logic Cells)". How can I calcuate Logic cells from information available in Map report?


********** Logic Utilization: Number of Slice Flip Flops: 4,288 out of 84,352 5% Number of 4 input LUTs: 7,880 out of 84,352 9% Logic Distribution: Number of occupied Slices: 5,150 out of
42,176 12% Number of Slices containing only related logic: 5,150 out of
5,150 100% Number of Slices containing unrelated logic: 0 out of
5,150 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 8,119 out of 84,352 9% Number used as logic: 7,880 Number used as a route-thru: 159 Number used for Dual Port RAMs: 80 (Two LUTs used per Dual Port RAM) Number of bonded IOBs: 500 out of 576 86% Number of BUFG/BUFGCTRLs: 5 out of 32 15% Number used as BUFGs: 5 Number used as BUFGCTRLs: 0
**************

Thanks in advance, Muthu


Until recently comparing 4-LUTs was the way to go. (Except for pathological cases) Now Virtex-5 with its 6-LUTs makes life more complicated.

Kolja

Using registers is probably the best way to go. You avoid the marketing mathematics of any given vendor, and to be honest with fmax being primarily limited by routing now, it seems that designs have very few levels of logic meaning the logic:register ratio is close to

1:1 for high performance IP.

As a counter example: The ration is almost 2:1 in the example given by the OP.

Kolja Sulimma

Ask the vendor for LUTs and Flops stats for your device. If they can't tell you, find another vendor.

-- Mike Treseler

6-LUTs? Sounds somthing like ORCA... (ATT -> Lucent -> Lattice)

JTW

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