Hi everyone,
While trying to build a simple VGA driver, I'm running into trouble getting my video-ram (actually, sample ram) to be synthesized as a dual port block-ram - it keeps wanting to use up 25% of my LUTs. I've tried to describe the BRAM as instructed in the xst.pdf documentation, but as soon as I try to read out the BRAM, the Synthesizer turns it into distributed RAM. I wonder if anyone would be so kind as to help me understand why?
The circuit consists of an 8 bit sampler which produces 2's complement data. It is connected to my Spartan-3 kit and I want the data to be displayed by the VGA port, as a primitive oscilloscope - just to verify that I'm getting valid data from the sampler. The display is generated by comparing the current vertical position against the sample ram contents for the current horizontal position, and drawing a pixel if they match - repeat for every position as the VGA display is scanned. This would undoubtedly benefit from more advanced concepts like double-buffering, but I'm slowly working my way up to that.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL;
entity main is Port (clk: in STD_LOGIC; sample: in STD_LOGIC_VECTOR(7 downto 0) red, green, blue: out STD_LOGIC)); ... end main;
architecture Behavioural of main is
type bram_type is array (511 downto 0) of signed (7 downto 0); signal BRAM: bram_type; signal BRAM_addra: unsigned (8 downto 0) := "000000000"; signal BRAM_addrb: unsigned (8 downto 0) := "000000000"; signal vert: unsigned (9 downto 0) := "0000000000";
process(clk) -- Read data from the sampler begin if(clk'event and clk='1') then ... BRAM(to_integer(BRAM_addra))