BRAM synthesis question

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Consider a fifo.

-- Mike Treseler

see

The read operation from a BRAM needs to be clocked. Either feed the read address through a register before using it to index the RAM, or register the output of the RAM. Either of these result in a 1 clock delay between the read address and the output data. There are code templates online in the XST users guide. Hope this helps.

Hi Paul, Yeah, if you look at your code, you're trying to do an asynchronous read. I suggest you try simulating your design and also a design where you instantiate a block ram. You'll be able to compare and see clearly what the block ram does. HTH., Syms.

This is not the first time that someone has tried to read the BRAM asynchronously. I have posted many times, and also inserted a sentence into our documentation that "nothing happens without a clock". Any ideas how we can spread this important (and non-obvious) information even better and wider??? Peter Alfke, Xilinx Applications

Hi Peter,

Just rename your component from BRAM to BSRAM ! Synchronous RAM !

As a ROM based on BRAM should be renamed by BSROM. (It is not regular to have synchronous ROM, but yes it is synchronous ( need CLK clock ) too when based on Xilinx BRAM )

Regards, Laurent

The problems I see in this newsgroup are a result of hdl designers continuously reinventing templates to infer a block ram by trial and error.

If I worked for Xilinx I would write an ap note in vhdl and verilog for a useful application example that infers block ram from code, and then reference that example in all related documents.

Feel free to use my public template if you like:

-- Mike Treseler

sorry but you may describe LUT as asynchronous ROM ? -> No Clock !

My 0.02

Laurent

This is an FPGA is it not.

Nothing in an FPGA happens without a clock.

Why would anyone think that BRAM would operate differently ??

My .02

donald

A world wide advertising campagne include TV commercials?

"And now a serious message from our Xilinx Jedi masters: use the clock!"

My mistake was not realizing that - of course - the data on the BRAM are not available instantaneously, but will be available at the next clock cycle, hence the need to register them. I mistakenly thought 'hey, this process block has a clock in its sensitivity list, so why is XST still claiming I'm using it asynchronously?' So I was not "tryin to read the BRAM asynchronously" as Peter wonders, just not having any idea what I was doing ;-)

Thanks for the many helpful replies.

Regards. Paul Boven.

donald wrote: (snip)

Where does this come from? There is no reason one can't do designs that don't use any FF's in an FPGA, though there is a strong incentive to use them.

Because that is the way traditional SRAMs work and people get used to using them that way. Also, most ROMs.

-- glen

Except that SRAM traditionally means Static RAM, so one might still not notice. How about BSyRAM?

-- glen

Hi Peter, When the synthesis software itself warns the user "The RAM will be implemented on LUTs because you have described an asynchronous read" and they still don't get it, I'm struggling to see what would be of further help? Cheers, Syms.

it's all (public) available:

- XAPP463 ("Using BRAMs in Spartan-3 FPGA") applies also for virtex-2 and with some additions/modifications for the newer virtex parts.

- In the xilinx "synthesis and simulation guide" chapter 4, page 152 pp, there are some (usefull) generic HDL code examples: How to implement a "generic BRAM" in VHDL and/or verilog.

WD