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infer block ram with mismatched port width

hi

i have a question on how to infer a block ram with mismatched ports. as far as i found out with google and the xilinx manuals this is how to infer block ram with matching ports in read first mode:

architecture syn of spi_memory_dp is type ram_type is array (63 downto 0) of std_logic_vector(15 downto

0); shared variable RAM : ram_type; begin process (CLKA) begin if CLKA'event and CLKA = '1' then if WEA = '1' then RAM(conv_integer(ADDRA)) := DIA; end if; DOA
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u_stadler
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nteger(ADDRA)) :=3D DIA;

nteger(ADDRB)) :=3D DIB;

I don't believe port width mismatches can be inferred yet through any synthesis tool. I asked about the capability a few years ago with the Synplicity synthesis products and found the support was not present and not planned.

If you want native port mismatches, you'll probably have to instantiate your memory blocks.

- John_H

Reply to
John_H

  1. Infer 4 dual memories that are each 8 bits wide (i.e. the width of the smaller port, in this case the 'B' side).
  2. Use the lower two bits of the B side address gated with the 'B' side write enable to generate 4 individual write enables for the above mentioned 4 dual port memories.
  3. The 'A' side write enable goes to each of the four dual port memories.
  4. During a 'B' side read, read from all 4 memories in parallel and then again using the lower 2 'B' side address bits, mux the appropriate byte to the 'B' side data out port.

There are other ways of doing this but the above is fairly forward to follow.

The key ideas here are:

- If you want to use FPGA internal memory and it doesn't happen to support mismatched data widths, then you have to instantiate multiple smaller memories that have a data width that matches your smaller data width.

- Wrap logic around those multiple memories to give the whole thing the appearance of implementing dual port with mismatched data width sizes. Kevin Jennings

Reply to
KJ

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