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avnet virtex-5 lx eval kit ddr problem

We have two of these boards (with the LX50 ES), and both failed the DDR memory test with a build from the Base System Builder. We downloaded the test designs from the Avnet Design Resource Center, and these would sporadically fail.

We looked at the datasheet for the MT47H16M16BG DDR2, and noticed that the acceptable frequency range for the DDR is between 125MHz and

200MHz. The BSB design uses 125MHz, and according to our FAE, the test design uses 200MHz. Apparently our boards are marginal at both these extremes. We modified the clock generator in the BSB design to set the clock to 133MHz and 150MHz, both of these designs passed the memory test.

As an aside, when I recompiled my EDK libraries for 9.2, I told it not to recompile any deprecated cores. Now it looks like there are only PLB cores availible, is Xilinx phasing out support for OPB?

We are using EDK/ISE 9.2 with the latest web updates.

Reply to
mikechin2000
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All Avnet boards go through a functional test prior to shipment. The functional test for this board is available under "V5LX50 Evaluation Test Files" at

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You could try this test. If you have found some marginality with your boards, then please send your test case to snipped-for-privacy@avnet.com.

See the following Xilinx Answer Record for the status of OPB:

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Bryan

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Bryan

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That's exactly what I did. I followed the instructions in the User Guide about programming the PROM with the functional test bit file. I get the prompt and various test option choices, they all seem to work except the DDR memory test.

I am trying to get our FAE to come out and see this for himself.

Thanks for the tip re OPB, we've had misgivings about the Xilinx implementation ever since we had sporadic and unfixable problems with multiple OPB masters. The same designs morphed into PLB masters seem fine.

Mike

Reply to
mikechin2000

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