Field-Programmable Gate Arrays

power supply noise margin

What noise margin should a power distribution network be able to delivery on the 1.2V, 2.5V and 3.3V supply for a Sparta...

1 comments posted 18yrs

posted by kislo02

1 comments posted 18yrs posted by kislo02

Need help on ASIC/ASSP FGPA-based prototyping and verification survey

Hi all. I'm running a brief survey on "ASIC/ASSP (FPGA-based) prototyping and verification tools and pratices." If you...

0 comments posted 18yrs

posted by jblyler

0 comments posted 18yrs posted by jblyler

xsa-50 issues

hey guys, i have an xsa-50 board by xess. i ran into some issues when trying to test the board using the GXTEST softwar...

1 comments posted 18yrs

posted by uraniumore235

1 comments posted 18yrs posted by uraniumore235

Programming XCR3064xl - voltage at output stuck at 0

I am programming Xilinx xcr3064xl device: http://www.xilinx.com/support/documentation/data_sheets/ds017.pdf I use the s...

7 comments posted 18yrs

posted by xc3064

7 comments posted 18yrs posted by xc3064

value of the weak pull up resistor on IOBs of Virtex5

Hi, Virtex5 datasheet state that there is a optional configurable weak pull-up/pull-down resistor on each IOB. What is...

2 comments posted 18yrs

posted by togoli

2 comments posted 18yrs posted by togoli

Is Virtex 4 supported by Jbits ?

Hi ! Is Virtex 4 supported by Jbits ?

1 comments posted 18yrs

posted by swissiyoussef

1 comments posted 18yrs posted by swissiyoussef

How to input an analog signal to FPGA board for processing?

Hello, I am a beginer and have a basic question. My project implemented on FPGA board (which is Spartan3E-1600 Microbla...

7 comments posted 18yrs

posted by vladimir.v.korostelev

7 comments posted 18yrs posted by vladimir.v.korostelev

has anyone made PLB_DDR work with 1Gb DRAM chips?

I have a design that consists in part, of the DDR interface from the ML403 board, but with two of these 1Gb DDR parts:...

0 comments posted 18yrs

posted by jcc

0 comments posted 18yrs posted by jcc

RLC package parasitics

In the IBIS model i can find the package parasitics R_pkg, L_pkg and C_pkg ... but what does these values represent? is...

2 comments posted 18yrs

posted by kislo02

2 comments posted 18yrs posted by kislo02

how to set trigger in ChipScopePro for this

Hi all, I have an application where my data refreshes every 10 seconds...It takes so long as I am doing some sort of an...

4 comments posted 18yrs

posted by pratap.iisc

4 comments posted 18yrs posted by pratap.iisc

Xilinx ML507 evaluation board (V5FXT70)?

A past google-search revealed Xilinx employees saying this board will be equipped with a Virtex5/FXT70. From what I rem...

0 comments posted 18yrs

posted by tsiuser

0 comments posted 18yrs posted by tsiuser

getting samples from an RF board onto the system

hi, I have got an RF board (antenna+ADC+Some signal processing boxes on a board). The output is a 2bit data and a clock...

1 comments posted 18yrs

posted by vittal.patil

1 comments posted 18yrs posted by vittal.patil

USB full speed final project proposal

I invite you to use free code of a USB full speed project as final work for diploma. The site includes some description...

0 comments posted 18yrs

posted by beky4kr

0 comments posted 18yrs posted by beky4kr

Conversion from VERILOG READMEMB to INTEL HEX

Conversion from VERILOG READMEMB to INTEL HEX http://bknpk.no-ip.biz/readmemb_to_intel_hex/readmemb_to_intel_hex.html

0 comments posted 18yrs

posted by beky4kr

0 comments posted 18yrs posted by beky4kr

udp receive problem under nios

Hi ,everyone,now I use the NicheStack tcp/ip stack for sending and receiving the udp packets, the hardware platform is...

0 comments posted 18yrs

posted by bjzhangwn

0 comments posted 18yrs posted by bjzhangwn