Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Conversion from VERILOG READMEMB to INTEL HEX
Conversion from VERILOG READMEMB to INTEL HEX http://bknpk.no-ip.biz/readmemb_to_intel_hex/readmemb_to_intel_hex.html
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15 years ago
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udp receive problem under nios
Hi ,everyone,now I use the NicheStack tcp/ip stack for sending and receiving the udp packets, the hardware platform is as follows,cyc-II 70 ,nios-ii,lan91c111 and so receive code is as follows. void...
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15 years ago
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ISE 9.2 - how do I extract component/slice placements for locking down a design?
Is there any NGD reader which can extract placement information? I know I can use FPGA editor and go through all the primitives, one by one, but this would be a mamoth task! Any ideas?
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15 years ago
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Vritex2PRO: LVDCI for inputs?
Hi, I am using Virtex2Pro, and I have assigned LVDCI IO standards for all my LVCMOS receivers. I was wondering if LVDCI has any significance for inputs. For outputs it adds a series termination...
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15 years ago
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Xilinx Platform USB Cable II
Hi I have intended an upgrade to Xilinx 9.2 or higher from version 7.1. With this newer versions my programming cable is no longer supported. So I am thinking of buying a Xilinx Platform USB Cable II....
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15 years ago
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5 V oscillator output to GCLK
Hi, I am using a Spartan3 xc3s1000-4 fg456 FPGA. I have an oscillator which gives clk output at 5V p-p swing. I am using the FPGA in LVTTL mode which works on 3.3 V signaling. Is it OK to feed the 5V...
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15 years ago
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SDIO CRC7 + VCD waves
The SDIO standard defines two kinds of CRC. CRC7 for command and CRC16 for data. This code is a CRC7. The module is checked via a SDIO generator. The SDIO slave is capable only in responding to the...
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15 years ago
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AHB and APB master VHDL generator
This project demonstrates an easy way to create AMBA masters and slaves. It includes an AHB master, AHB slave, APB master and APB slave. http://bknpk.no-ip.biz/LEON/AHB_APB_leon/AHB_APB_leon.html
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15 years ago
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Anyway to secure a Xilinx NGC file ?
Hi, Is there anyway to secure a Xilinx NGC file from being reverse engineered ? Xilinx has a ngc2edif utility to convert the binary ngc file into a readable netlist. Still work of course but makes it...
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15 years ago
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Spartan 3 Mapping Problem
So, I'm busily poking around at a Spartan 3 design, and can't get my latest iteration of things to build properly. I've got all my pin locations defined, but make no recommendations to the tools as to...
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15 years ago
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Virtex XCV1000E-6FG860C
Need help on a Virtex XCV1000E-6FG860C . I am short 500 pieces and the only parts I see are coming from China brokers. Please call with any quantity that you can supply. I need them ASAP. Jon E....
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15 years ago
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ML300 evaluation board broken?
Hi After two years I am back trying to use the ML300 evaluation platform for some FPGA programming. I connected the MultilinX cable to the P114 connector in order to program the board over the JTAG...
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15 years ago
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Quartus 7.2 and PCI Express
Good day! Have: -Quartus 7.2 SP3 -Megacore IP SP2 Need: -PCI Express. But I have only In Quartus/tools/license Setup/MegaCore functions I see PCI Express. And Quartus give a warinig: using OpenCore...
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15 years ago
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Dual rank DDR2 memory for Xilinx ML410 board
Hi, all, I am trying to make a PowerPC system with dual rank DDR2 on Xilinx ML410 board. When I set 2 banks and different addresses for the 2 banks in the plb_ddr2, some output signals about the DDR2...
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15 years ago
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EDK for spartan2?
Hi, We have a PC104 board with a spartan2 device. I tried to compile a microblaze system for this device but got the error "not supported for architecture spartan2". I've seen however that in the past...
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15 years ago
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