I am trying to make a PowerPC system with dual rank DDR2 on Xilinx ML410 board. When I set 2 banks and different addresses for the 2 banks in the plb_ddr2, some output signals about the DDR2 controler are increased to 2 bit due to the increase of the number of the memory bank (e.g. DDR_CSn_pin). But I can not find information about which I/ O pins I should connect these extra bits. Could anyone give some hints for this?
Thank you in advance,