Latest threads in Field-Programmable Gate Arrays

FIR in FPGA

Hai, 1.Can i set the clock frequency of the FIR filter at any frequency i want... but pretty much higher than the sampl...

3 18yrs

fazulu.vlsi

3 18yrs fazulu.vlsi

RGB video panel

Hi everyone,i am trying to display a video on a rgb leds.The leds would be connected to the fpga what i was concerned a...

1 18yrs

ankitanand1986

1 18yrs ankitanand1986

Xilinx Clock Doubler

I have a 10MHz clock but needed a 20MHz clock speed. I used two asynchronous clear flip flops with a series of buffers...

13 18yrs

grant

13 18yrs grant

Are FPGAs headed toward a coarse granularity?

I was reading about the MathStar FPOA devices and I started thinking about parallels between the architectural advances...

9 18yrs

gnuarm

9 18yrs gnuarm

FIFO verses RAMB

In the Xilinx Virtex 4 architecture, does anyone know when you instantiate a FIFO using the FIFO16 blocks does the FIFO...

1 18yrs

erik.k.anderson

1 18yrs erik.k.anderson

HDL - simulation vs synthesis

I run Xilinx ISE v10.1 and use VHDL. I have put together a fairly small circuit that merely sends out solid colors and...

4 18yrs

jared.pierce

4 18yrs jared.pierce

Virtex 2 with PLB_v34 and EDK 10.1

Hi, I'm trying to build a system for a XC2V6000 FPGA. The problem I have is that I have to implement a PLB. But the PLB...

2 18yrs

rmeiche

2 18yrs rmeiche

error when 'generating simulation hdl files' in xilinx xps

hi, does anyone know how to solve this error when selecting 'generate simulation hdl files' in xps (xilinx edk 9.1): --...

3 18yrs

fatfpga

3 18yrs fatfpga

Sequentially syncrhronous

Sorry, Guys. We're not quite done yet with the quadrature encoder. I tried to rewrite it as a synchronous process. The...

19 18yrs

boat042-nospam

19 18yrs boat042-nospam

JTAG + PROM error!

Hi, I have the problem that I can't communicate with my Xilinx XCF04S PROM through JTAG. The circuit setup is a "3.3V M...

7 18yrs

jidan1

7 18yrs jidan1

Need comparison table about Xilinx ISE WebPack 10.1i vs ISE Foundation 10.1i

Does anyone have comparison table about Xilinx ISE WebPack 10.1i vs ISE Foundation 10.1i ? Because I was confused by the...

2 18yrs

aan.woodz

2 18yrs aan.woodz

Mathstar plans to discontinue FPOA development

News: "As it seeks a buyer, MathStar said it plans to discontinue its field programmable object array (FPOA) chip devel...

4 18yrs

no.spam

4 18yrs no.spam

HWICAP initialization

hi all, I am trying to use HWICAP to configure certain LUTs , I guess that starting with the examples from XILINX will...

2 18yrs

fatma.abouelella

2 18yrs fatma.abouelella

FIR filter o/p width

Hai, Is there any formula or general rule to set output width of FIR filter given its input ,coefficients width and num...

1 18yrs

fazulu.vlsi

1 18yrs fazulu.vlsi

Ph.D Student

Good morning. I am currently seeking any publication of my work with FPGA devices, especially for obtaining Ph.D Studen...

3 18yrs

pbantunez

3 18yrs pbantunez

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