Field-Programmable Gate Arrays

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Xilinx Clock Doubler

I have a 10MHz clock but needed a 20MHz clock speed. I used two asynchronous clear flip flops with a series of buffers...
13 comments posted 18yrs
posted by grant
13 comments posted 18yrs posted by grant

Are FPGAs headed toward a coarse granularity?

I was reading about the MathStar FPOA devices and I started thinking about parallels between the architectural advances...
9 comments posted 18yrs
posted by gnuarm
9 comments posted 18yrs posted by gnuarm

FIFO verses RAMB

In the Xilinx Virtex 4 architecture, does anyone know when you instantiate a FIFO using the FIFO16 blocks does the FIFO...
1 comments posted 18yrs
posted by erik.k.anderson
1 comments posted 18yrs posted by erik.k.anderson

HDL - simulation vs synthesis

I run Xilinx ISE v10.1 and use VHDL. I have put together a fairly small circuit that merely sends out solid colors and...
4 comments posted 18yrs
posted by jared.pierce
4 comments posted 18yrs posted by jared.pierce

Virtex 2 with PLB_v34 and EDK 10.1

Hi, I'm trying to build a system for a XC2V6000 FPGA. The problem I have is that I have to implement a PLB. But the PLB...
2 comments posted 18yrs
posted by rmeiche
2 comments posted 18yrs posted by rmeiche

Sequentially syncrhronous

Sorry, Guys. We're not quite done yet with the quadrature encoder. I tried to rewrite it as a synchronous process. The...
19 comments posted 18yrs
posted by boat042-nospam
19 comments posted 18yrs posted by boat042-nospam

JTAG + PROM error!

Hi, I have the problem that I can't communicate with my Xilinx XCF04S PROM through JTAG. The circuit setup is a "3.3V M...
7 comments posted 18yrs
posted by jidan1
7 comments posted 18yrs posted by jidan1

Mathstar plans to discontinue FPOA development

News: "As it seeks a buyer, MathStar said it plans to discontinue its field programmable object array (FPOA) chip devel...
4 comments posted 18yrs
posted by no.spam
4 comments posted 18yrs posted by no.spam

HWICAP initialization

hi all, I am trying to use HWICAP to configure certain LUTs , I guess that starting with the examples from XILINX will...
2 comments posted 18yrs
posted by fatma.abouelella
2 comments posted 18yrs posted by fatma.abouelella

FIR filter o/p width

Hai, Is there any formula or general rule to set output width of FIR filter given its input ,coefficients width and num...
1 comments posted 18yrs
posted by fazulu.vlsi
1 comments posted 18yrs posted by fazulu.vlsi

Ph.D Student

Good morning. I am currently seeking any publication of my work with FPGA devices, especially for obtaining Ph.D Studen...
3 comments posted 18yrs
posted by pbantunez
3 comments posted 18yrs posted by pbantunez

impact / encrypted bitstream

Hi , i tried yesterday to configure my fpga with an encrypted bitstream . Using Impact 10.1 i didn't unerstand the way...
4 comments posted 18yrs
posted by swissiyoussef
4 comments posted 18yrs posted by swissiyoussef

signal value at power up

Here is my question/issue: say you have: y : out std_logic; signal x: std_logic; you don't assign any value to "x" but y...
7 comments posted 18yrs
posted by martstev
7 comments posted 18yrs posted by martstev