Phase / frequency detector types

The issue with phase/frequamcy comparators is that they must work and correct the error under all circumstances, with both frequencies widely different, and also with identical frequenceis, but a small phase difference. That limits the playing field. Many decades ago, Motorola created a circuit (I think it was calle 4044 or something like it) that did this job beautifully. I once converted this design into FPGA land, see

What you do with the bang-bang outputs is up to you. You can >

Hi, A small note of caution when using Peter's XAPP028 in Virtex II. As well as constraining the logic to the CLBs shown in the app note, make sure you specify a MAXSKEW attribute on the reference signal and feedback signal to the circuit. I use 100ps. Without this the circuit can occasionally malfunction depending on the place and route. (These are the signals called 'from VCO divided by N' and 'from reference frequency'.) There was no problem when this circuit was used on older FPGAs where the routing to the F and G lookup tables in a single CLB was guaranteed to have low skew. In Virtex II this is no longer the case and a single signal that goes to both the F and G inputs of a CLB can have significant skew if not constrained. This can cause the circuit of XAPP28 to misbehave. Of course it's not your fault Peter that those guys changed the routing from the original 3000 (I guess) design! Thanks for a good APP note I've used many times, maybe it needs a small update! HTH, Syms. p.s. I'm not sure which Xilinx families need the MAXSKEW, I use it always because it can't hurt. Also, make sure the signals don't connect anywhere else, or the MAXSKEW will fail. Replicate them if necessary.

Hi, Try

for a good read on PLLs. I'm thinking of using the design in chapter

12 with the XAPP0028 circuit minus the tri-states. Also, see XAPP250 for a similar PFD design. In XAPP250 use a delay between the 'AND' gate and the reset of the FFs to get rid of dead band. This delay allows both 'up' and 'down' to be on at once, so don't connect them together without a resistor at least! HTH, SYms.

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In most hardware designs, tri state is a way to lock a steady charge on the integrating cap, instead of always ramping it up or down, "galloping ghost" style. Applied that way, it reduces phase jitter.

Jerry

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Engineering is the art of making what you want from things you can get.
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Hi Jerry, I agree! The circuit in 'Dean's Book' I referred to doesn't use tri-states, it uses a diff amp integrator driven by the signals that would've driven the tri-states. This also prevents "galloping ghost", if I understand your terminology right!? As I learned from the 'book' this fixes (or can fix) problems with charge leakage from the tri-state, power supply noise on the tri-state drivers. It also means the spurs resulting because, typically, the integrated voltage isn't midway between the rails of the tri-state driver, are lower and more predictable. Syms.