comparator problem

Since you're posting to the FPGA newsgroup....

STOP IT !! Don't try to add analog components - however simple they may seem in concept - when you have the FPGA resources to give you what you need with very little overhead. You need a clock resolute enough to discern 8ms from undesired shorter values. Use this clock to count when 8ms is valid then generate your 64ms pulse with the same clock. No fuss no muss.

If you're trying to use the differential inputs to an FPGA as a comparator, keep in mind the voltage tolerances on the input to your circuit as well as the voltage driving the feedback. The tolerances on your resulting circuit will be sloppy and not necessarily repeatable.

I'm not sure I understand what you are doing, but if I get it right, your input pulse goes from 0.5 volts to -2.5 volts and 8 uS later returns to 0.5 volts. You want an output pulse starting when the input pulse goes low and lasts for 64 uS. If this is right, I would say you need to swap the feedback resistor with the RC. Actually, you don't need an RC, just a C will do.

But this circuit will have all the problems with noise that the 555 timer has and may even be worse since noise on the comparator output can affect your circuit.

BTW, where did you get a 2248.5k ohm resistor? What is that, .001% tolerance?