Hi All,
I'm trying to synthesize the folllowing VHDL file with the Xilinx WebPack tools. I'm synthesising for a XC3S200 chip. When I run XST it generates one 256 bits serial register and assigns outD and outD1 both to the same output of the shift register (I checked with the RTL schematic viewer). Changing outD1
The ISE schematic viewer didn't show you everything. If you implement the design and look at the ncd file with the FPGA editor, you will see that outD and outD1 come from two different places.
Hi,
Thanx for your reply
As far as I can see FPGA editor is not part of the WebPack tools so I can't use that. I've tried following lines with the floorplanner, but automatic place and route leave all SRL16 unplaced and unrouted (that is an other mistery not yet clear to me why that happens or rather doesn't happen). Is this a bug in the ISE schematic viewer that it doesn't show the correct schematic? I've tried switching off the SRL16 generation and then I get the correct schematic (although with 256 seperate FF ofcourse)
I understand that part. I will try to get both (28) and (27) to see what the tool tries to do in that case. Because that should split the shift register too.
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