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Re: speeding up quartus
- 08-08-2003
- Mike Treseler
August 8, 2003, 11:39 pm
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Gosh. I wish I had a sysadmin. Any openings? :)
One hour is not bad for synthesis and place+route
on a medium sized FPGA.
I haven't even tried the "logic-lock" place+route locker because
things change too much and I don't do that many place+routes.
You should turn on "smart-compile" to save the cache.
Hard drives are cheap.
A simulation recompile and rerun only takes a few minutes.
You might suggest the designer spend more time on the
testbench and less in synthesis/place+route.
-- Mike Treseler
Re: speeding up quartus
forum for the last few months.
For years it seemed that only Xilinx cared about their user community on
here so its nice to see the support. Kudos to Paul, Subroto et al. (and
continuing thanks to Austin, Peter et al from Xilinx)
Mike hit the nail on the head, most work should be done pre-synthesis. Of
course the Altera product (or Xilinx) doesn't really lend itself to doing
this by itself. I'd recommend Active HDL (www.aldec.com) though others swear
by ModelSim
You 'really' need a decent simulator to speed the overall design process.
Paul
unreasonable
fitter
past
lock
Re: speeding up quartus
Paul,
The device is an EP20K, 1500EBC652-1X, the user said that he
is using <20% in logic and <60% in memory. We've discussed your
info and have decided that the first step is, as you recommend,
upgrading to 3.0.
The reason for the P&R is that we do not have any real lab
equipment and the user is bringing signals out to the 3 on-board
LEDs. I take it that this requires a new P&R everytime.
Don
The device is an EP20K, 1500EBC652-1X, the user said that he
is using <20% in logic and <60% in memory. We've discussed your
info and have decided that the first step is, as you recommend,
upgrading to 3.0.
The reason for the P&R is that we do not have any real lab
equipment and the user is bringing signals out to the 3 on-board
LEDs. I take it that this requires a new P&R everytime.
Don
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