Xilinx System Generator

Hi ALL! I started large DSP project by Xilinx System Generator.

1.I have some problems in my design with "loop back". I inserted "Use explicit sample period" for all components in loop. But in simulation i have : "The Relational Block received data in an indeterminate ("don't care") state" . Design have no errors - VHDL Netlist Generation - OK . Any idea to help simulator ? I have some attempts by inserted Register with Reset - no good results.

  1. Who have good experience with Xilinx System Generator ? I need in your opinion. Is this Soft equal to new funny toy or real CAD product ?

Thank you. Alexander Litvinov

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I have encountered this problem. Trying to remember how I solved it ... I think that I had to create a Valid Out port on the "source" component, connected to the Enable input port on the "destination" component.

I have created some incredibly complex designs with it. I know signal processing, not VHDL, so I can say that it allowed me to do things that I could not otherwise do without a tremendous investment in time and effort.


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Greg Berchin

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