Hi ALL! I started large DSP project by Xilinx System Generator.
1.I have some problems in my design with "loop back". I inserted "Use explicit sample period" for all components in loop. But in simulation i have : "The Relational Block received data in an indeterminate ("don't care") state" . Design have no errors - VHDL Netlist Generation - OK . Any idea to help simulator ? I have some attempts by inserted Register with Reset - no good results.
- Who have good experience with Xilinx System Generator ? I need in your opinion. Is this Soft equal to new funny toy or real CAD product ?
Thank you. Alexander Litvinov