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Xilinx System Generator, Gateways not implemented

Hello,

I have problems with gateways in System generator 6.1.1, ISE 6.103, Matlab 6.5.1. I use a XtremeDSP Development Kit II With Virtex 2 XC2V3000-4fg676 and want to connect the AD and DA-converters, but this failes.

So I made a simple test file, only 1 line, type boolean, between 2 Gateways. I can generate the ISE project. In ISE I try to implement, but the 2 signal names of the gateways cannot be found.

Since gateways are the only way to connect pins with the circuit, no pins can be connected at all in Virtex 2? This cannot be possible, what is wrong there?

Xilinx hotline seems to have holiday :-(.

Regards, Winfried

Reply to
Winfried Salomon
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When you double-click on an output gateway, does "Translate into Output Port" have a checkmark by it? If not, then the port, and everything connected to it, is removed by the optimizer.

Greg

Reply to
Greg Berchin

Hello Greg,

the checkmark is set, but nevertheless it doesn't work. In the generate process there is no error message. But in ISE the synthesizing process stops with errors:

ERROR:Xst:1370 - Line 6: Signal name gin2 not found in design. ERROR:Xst:1370 - Line 7: Signal name gout1 not found in design. ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:Xst:1341 - XCF parsing failed ERROR: XST failed

But I can see the "optimized" circuit in RTL-viewer. Very strange, there are 8 input and 8 output data lines, in between 8 D-FFS FDE. In Simulink I have only one line type boolean. When I change line type to 1 bit unsigned integer, it changes nothing. I don't know what to do.

Regards, Winfried

Reply to
Winfried Salomon

Sorry, your problem is unlike anything I've ever seen with System Generator. Probably best to get in touch with Xilinx.

Good luck, Greg

Reply to
Greg Berchin

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