Help with ram controller on Xilinx Spartan IIE

Hi together.

I'm relatively new with FPGAs and I have no experience with rams. Now I'm working on a ram controller for a MEMEC FPGA board with a xilinx spartan IIE (@100 MHz). It should be a very simple module, and speed is not very important, because the data to be written come at a low frequency.

So I designed a state-machine, which handles the signals. Unfortunately it does not work, although in the simulation the signals have the correct form. At this point I have some questions:

1.) Do I have to instantiate special IO-buffers for the ram signals? The synthesis creates IO-Buffers but I'm not sure if it is OK to do it this way.

2.) The datasheet of the ram modules show that the signals must be valid for a defined time, before and after the posedge of the ram clock. Is it an appropriate way the set up the signals at the posedge of the clock and use the negedge for the ram?

3.) Do I have to set NOP commands for the ram? The timing diagrams show NOPs, which have a special operation command. On the timing diagram for the AC parameters there are no NOP commands show, simple no command is set. How do I have to handle this?

I'd really appreciate every piece of advice!

Thanks in advance. Michael

Reply to
Michael Pieber
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What kind of ram are you talking about here? DDR SDRAM, for instance, has quite tight timing constraints, and requires a carefully considered clocking strategy. SRAM on the other hand may well be a lot simpler, depending on the type.


Reply to
Jeremy Stringer

It is a "normal" synchronous DRAM (Infineon HYB25L128160AC).


Reply to
Michael Pieber

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