Xilinx: Clock speeds 420MHz+ tested in Spartan-3


There have been different claims of being faster and bigger from different sides. The best thing to know it for real is to perform actual testing of the silicon (and not to believe the marketing stuff), I can present some results of actual measurements:

DUT: Spartan 3S1500-4C-fg676 ES, measured normal ambient temperature

LUT propagation delay as measured (measured was a t_LUT+t_switchbox): 595 ps

Xilinx datasheet says 610 max propagation delay what matches very well with the actual measurement, I would estiamate switcbox delay of 30-60ps so the resulting LUT delay is about 10% than the max in datasheet.

Measured clock frequency where the logic in the FPGA fabric was operational:


Some notes:

420MHz is not the limit, we just did not do any tests at higher frequencies.

the 420MHz clock was not derived from DCM (its above the recommended limits of DCM), measurements how high can DCMs actually go was not done, most likely way over 420MHz.

fanout and/or routing of the high clock really is critical :) but that is to be expected, we did see some erratic behaviour when the 420MHz was travelling longer distances in the FPGA (1/3 of the length of the array).

the test design was run with ABSOLUTLY NO timing constraints applied, all the critical path components where locked down directly to FPGA slices.

Please use the test results with care, the actual perfomance that can be achived is totally desing dependant. Our measurement just shows that using signal as high as 420MHz is defenetly possible in the lowest speed Spartan-3. So the fabric can go really high if the tools do the their job correct.

All the results are from actual measurements with real silicon, so not biased from any marketing claims or based on unverified data.


PS I could do some measurements to compare the competitor parts as well. All I need are DUTs hardware for measurements. The test designs and measurement appliction software can be used for any FPGA/PLD.

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Antti Lukats
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AND theres a -5

Cheers, Alf

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"Unbeliever" schrieb im Newsbeitrag news:42d7bee4$0$13477$ snipped-for-privacy@news.optusnet.com.au...





Hi Alf,

well the -5 would cut the LUT delay by some 12% maybe.

there is one important correction to my original report, I assumed the DCM can go eveb higher than 420MHz, thats totally wrong!!!

Datasheet says max FX out is 280MHz, actual measured max useable DCM output (in DFS mdoe) is 250MHz, at 275MHz the DCM output was some random trash,

275MHz appears in output also once in a blue moon, but there is no stable output clock, testing was done with 75MHz input clock and 11/3 multiplier/divisor.

this is a little weird as to my question about the DCM with V4 Xilinx answer was that the DCM actually works way beyound the settings that are possible in the coregen (same as in datasheet), I assumed the same statement to apply for S3 as well, but that isnt the case. Even the datasheet max is not working, well I am measuring early ES silicon, the DCM characteristics may be better for production silicon.


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Antti Lukats

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