I am looking at the data sheet for the Spartan 3 parts trying to figure out how to configure them. It seems like it is the same as most of the other families, but there is one note that I don't completely understand. Section 3, page 12, has the following text...
Figure 5: Waveforms for Master and Slave Parallel Configuration Notes:
- In a given CCLK cycle, when RDWR_B transitions High or Low while holding CS_B Low, the next rising edge on the CCLK pin will abort configuration.
This is not exactly the same as XAPP176 describing the Spartan II configuration, page 14...
While CS is High, the Slave Parallel interface does not expect any data and ignores all CCLK transitions. However, WRITE must continue to be asserted while CS is asserted. If WRITE is High during a positive CCLK transition while CS is asserted, the FPGA aborts the operation.
In the first case it sounds as if the abort condition is created by CS- being low and an edge on the RDWR- signal followed by a rising edge on CCLK (without making it clear if this also has to be during CS- low).
In the second case, it is just the state of the two signals, sampled at the rising edge of CCLK which will create an abort.
If I am trying to use the CS- WR- and IO signals from an MCU to control this, the difference between these two descriptions is significant. Am I making this more difficult than it is? Can I connect the signals as shown below and make this work ok?
MCU FPGA Write NO
--- ---- Byte Write CS- RD_WR- ----_______------______--- WR- CCLK -----_____--------____---- IO CS- -_____________------------
The other thing I am not clear about is how to use these same signals after configuration. It looks like I have to set "persist" to off if I want to put these signals on the MCU bus after config in order to have a bus interface to the chip. But if I want to perform partial reconfiguration, I think I have to have "persist" set to on, no? Does this mean I will have to double up on all these signals, one for (re)configuration and one for operation?
I seem to recall that the Lucent chips allowed you to use the MCU interface after configuration. Do the Xilinx chips have that as well?