Xilinx S3 I/O robustness question

lecroy · 2003-09-08T13:20:47+00:00

I have spent the last 60 days trying to get an answer from Xilinx ontheir new S3 devices. During a review, it was stated that the new S3swere very sensitive to transients on the I/O pins. Because they made apoint to mention this during the review, I posed the followingquestion to Xilinx:"If we look at the incident versus reflected energy and tune the stub(trace)for a worst case match is it possible the driver could be damaged orthechip lock up due to the reflected energy?""The circuit would be as follows:Spartan III Output ------------------------------ Tunable Stub"I wonder if anyone in this group has asked this question and what wasthe responce from Xilinx?

Sep 08, 2003 63 Replies

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Austin Lesea 22 years ago

Rick,

The IBIS models are based on the foundry spice models, which are pretty mature now, as the same transistors used for the IOs have been manufactured now for almost a year.

Just because others have absolutely lousy IBIS models out there does not mean we do: We continually check the quality of the models. Yes, Spartan 3 has preliminary models but only because it is not released to production yet

-- it is still int he ES phase. This allows us to make changes easily as we discover issues. So far, no issues with IBIS.

Aust> lecroy wrote:

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rickman 22 years ago

Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX

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lecroy 22 years ago

From a Xilinx S2 IBIS model.. Note " .... this model is considered preliminary as it has not been verified by actual silicon measurement." And this is an old part. How good do you think Xilinx models are for the S3??

[Disclaimer] The data in this model is derived from SPICE simulations using modeling information extracted from the target process. While a great deal of care has been taken to provide information that is accurate, this model is considered preliminary as it has not been verified by actual silicon measurement. Treat the data in this model as preliminary until actual silicon verification is performed. [Copyright] Copyright 2000, Xilinx Inc., All rights reserved

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Austin Lesea 22 years ago

Standard disclaimer.

We don't seem to get around to removing the caveats.....I'll look into that.

All parts once they are in production have been verified in MY lab.

By the way, folks have asked about duty cycle distortion in the outputs, and IBIS models will allow you to simulate the FAST/STRONG corner and then the SLOW/WEAK corner. You can imagine that the rise vs. fall times could be (absolute worst case) that different. Godd thing to check when you want to know "is this standard fast enough for my xxxx application?"*

Austin

This does use the low vcc, low temp, high vcc, high temp as part of the corners (as well as the process variati> > Rick,

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