Xilinx S3 I/O robustness question

The traces may not actually be individual circuits! While Austin (and others, including myself) advocate SI simulations to show the effects of terminations on line ringing and what not, what can _really_ bite you in the ass is crosstalk. In one particular case, there was an issue with crosstalk from a data bus affecting a nearby reset line. When a simulation was finally run, the problem was obvious.

So, yeah, I'd say that not bothering to simulate these lines because they weren't clocks and because "the signals can bounce around for a couple of ns" was a bad idea.

The time spent simulating upfront is well worth the investment. You simulate your FPGA logic, because you'd rather spend the time in front of the computer, rather than in the lab with a 'scope probe? Same thing here, except that a board spin is a lot more expensive than reprogramming that ISP EEPROM.

Oh, yeah, the 'scopes and probes required to really see these types of problems in the lab cost more than the SI software.

Perhap Xilinx are simply erring on the side of caution. They're informing the user of potential issues when they can be dealt with -- in the design phase -- rather than when boards are RMAed and customers are pissed.

In any event, I think Austin's tone was one of frustration -- after all, he's trying to help you! Basically, he's saying that if you do the simulations up front, your board can be designed such that these potential problems don't turn out to be actual problems.

Reply to
Andy Peters
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Ringing is not the cause of crosstalk. Crosstalk is coupling of the primary wavefront coupling to adjacent traces due to proximity over excessively long lengths. No amount of simulation will correct a problem if you don't understand what is going on.

But you are making assumptions about the circuits I am building. The original issue was the fact that the Spartan 3 chips are sensitive to even short term overvoltage due to ringing. Like I have said, I have never seen this in any data sheet until now. All the chips I have worked with either have specifically indicated that there would be no problem of damage due to small, short term transitions outside the rated voltage spec, or this was stated when the manufacturer was contacted. The Spartan 3 chips are the first I have heard of this being specifically contraindicated.

He is not the only one who is frustrated. My questions were not about the issues of designing for SI, but about the sensitivity of the Spartan

3 chips to damage from ringing. His replys are not responsive to my comments and questions. I can do a few simple calculations to get worst case numbers for ringing on a 6" trace. I don't need to use expensive software that does the same calulation with a few extra variables thrown in that simply fine tune the calcs.

The other reason that I can't simulate the signals up front is because the Spartan 3 in this design will be driving signals to multiple daughter boards that are not designed or even planned yet. Obviously this will have to be dealt with at the design level when the time comes.

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rickman

I also haven't heard of this before. But then, I haven't used 90nm parts before. Perhaps this is the way of the future.

Allan.

Reply to
Allan Herriman

Hi Rick, Here are things that I agree completely with you on. "No amount of simulation will correct a problem if you don't understand what is going on." and "I can do a few simple calculations to get worst case numbers for ringing on a 6" trace.". Without first understanding what's going on, the simulator can be a dangerous thing. Garbage in, garbage out! I think it's absolutely vital to know what's going on or how will you be able to sanity check the results the simulator gives? cheers, Syms.

Reply to
Symon

I did not say that "ringing is the cause of crosstalk." I said that another SI issue that you ought to be concerned about is crosstalk. I then went on to say that, because of crosstalk, we saw that the badness on the data lines was being coupled to a reset line.

And, yes, simulation showed us exactly what was going on.

I'm sorry if I wasn't clear.

Like I said -- consider that Xilinx are erring on the side of caution. And, as Austin points out, one can minimize the possibility of this sort of potential damage by performing the appropriate SI simulations, and adjusting the layout as needed.

Again, his comments are that as chip geometries shrink and rise times get faster, one needs to consider SI issues everywhere. Erring on the side of caution.

You know your needs better than the rest of us; I can't argue with that.

Ah, but you can, if you can obtain a model of the connector you're going to use, and assume that you've got a perfect load on the other side. Better than nothing. You can also deviate from "perfection" and see the effects on your board.

Reply to
Andy Peters

I have been away, but was glad to see people are starting to talk about this possible issue with the S3.

to the driver do to the

every one of the 200+ hotline

get multiple answers...) It

their mistakes, and improve

closing the loop!

Well, like I had stated early on, I had spent about two months working the channels at Xilinx trying to get an answer, starting with the person who made the original comment about it being a problem. I never opened a case with the hotline. I have never found them to be useful and it seems their only goal to it to close as many calls as possible, not help the customers. That's for a different topic.

output pin to a voltage that

really hard for the reflection

excursions are, an be sure they stay

Well, not like Mr. Pease, I have always been a big user of simulation as one tool. Certainly, not the last tool and I don't see it replacing the VNA any time soon as a way to get the 'real' picture of what is going on. But the question I always have when some one throws out the simulation card is how good is your model. When Xilinx released the IBIS models for the S3, how much data was it based upon? Have they continued to update the model as parts are being tested? How much do you trust it?

get the "final word" from the

Do I have a specific waveform, no. I am asking a general question about the S3. Just how sensitive it really is and what precautions do I need to take to make it work. Because each layout is different, the loading can be anything if you consider all of the failure modes.

Reply to
lecroy

That was some good reading! Thanks to everyone who had input on this subject.

I would like to know more details about how the S3 I/O models are being maintained. I can't seem to get Xilinx to keep up with their timing models in their own tools.

If the S3 really is that sensitive, I would not use simulation as the last word. While we have more "sensitive" boards tested at the supplier's, even this may no longer be "good enough" to validate the PCB. And if they hit 10% on their test pads I think they are doing good.

My big fear is that while we have been doing 1G digital designs for several years using ECL without any problems (well), as we migrate to putting these designs into faster FPGAs that we may loose reliablity. The best thing we could hope for is for the FPGA designers to make a quantum jump to 100GHz+ internal routing and take all the fun out of the layout. And while your at it, there are some other features I would like packed in there as well. Maybe I will live to be that old, but I don't think so.

Thanks again for putting some light on this.

Reply to
lecroy

lecroy,

See below,

Aust> I have been away, but was glad to see people are starting to talk

back to the driver do to the driver,

of the 200+ hotline CAEs to get

you get multiple answers...) It

their mistakes, and improve their

the loop!

Unfortunate. If you don't ask, you don't get an answer. Try it. If it doesn't work, let us (me) know. You must prefer doing everything the hardest way possible. We also do not appreciate the slamming of our hotline staff. Theya re all dedicated to helping our customers succeed, as that is what sells parts, not "closed cases." If a hotline engineer can not resolve the problem within a fixed amount of time, it is escalated. Once escalated, it then goes up the ladder til it reaches someone who can resolve the issue.

the output pin to a voltage that is

really hard for the reflection to

excursions are, an be sure they stay

You can not even probe, nor observe the points that are in question here. The VNA is a frequency domain tool, and unless you convert the S parameters into their transient form (done by some advanced simulators) you will learn nothing at all (even after simulating or trying to measure). "Real" only applies to this one part. What about the next one?

The test chips from UMC that had all of the transistors on them and characterized.

Yes. That is the procedure.

Better than the real silicon, which may be from any yielding corner, and not be representative of the worst possible cases (fast, cold corner, with hi-voltages for example. You can not buy a fast corner IO transistor version of the chip, you have to simulate it. Folks who submit their chips to a third party for IBIS models do their customers a terrible dis-service, as the model is only as good as the sample of chips sent, which is ususally terrible.

We must support our devices through accurate and useful models. Fact of life (and business).

The models are an IOU: that is what we tell you you will get.

get the "final word" from the

General Answer: simulate it, and make sure it meets yourt needs, and our operating and abs max specifications.

Already stated, if you exceed the abs max specs, you may find that more than .1% of the parts do not last the intended operating life. Good Signal Engineering practices will result in a robust design that will meet all goals, and all specs and last a long, long time.

A car manufacturer was once asked, "what is the safest way to use your vehicle?" The answer: "don't use it at all. Just park it, and walk away."

So ask questions that can be answered, like sending me a plot of what you think might be a problem. Or logging a call to the hotline (and then letting us know if you are not completely satisfied with the answer).

Failure mode is simple: the stress on the pmos output device when the IO pin is used as an input shall not exceed that stated in the abs max spec (4.05V for example on Virtex II Pro and Spartan 3, +3.75V abs max Vcco, and -0.3V abs max Vio on the io pin). If this stress is exceeded, it will eventually cause the IO to become leaky (ie > 10uA IOB leakage current spec will be violated). This increase in leakage may, or may not affect your system.

Simulate and you will see......

Reply to
Austin Lesea

If you go outside the limits with Vio and are current limited to 10uA will there be a problem? How about 100uA? 1mA?

Please excuse my ignorance on this stuff....

Reply to
Tim

Tim,

Since this is an input, there is no current going into/out of it (unless you go to the clamp diode limit).

So assuming that the diodes are not clamping, it is purely a voltage issue.

No ignorance here at all, the effect that is actually seen (with tests at >

4.5V) result in increased leakage, but no functional failure of the IOB (it still works, but does not meet the < 10uA IO pin spec).

This is the subject of research and PhD thesis material among the technology communities.

Aust> Aust>

Reply to
Austin Lesea

excursions are, an be sure they stay

That is a *very* important question. We have seen the timing files go through iteration after iteration of refinement. At what point can be believe that the IBIS models will be stable?

get the "final word" from the

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rickman

back to the driver do to the driver,

one of the 200+ hotline CAEs to get

you get multiple answers...) It

their mistakes, and improve their

closing the loop!

doesn't work, let us (me) know. You

appreciate the slamming of our hotline

I don't understand why you feel the need to shoot the messenger. The hotline staff of most companies is just as Lecroy described, eager to end the call as that is how they are evaluated. Xilinx is no exception and this has been noted here on more than one occasion.

This newsgroup is a place of all of us to share our experiences and opinions and I, for one, don't appreciate your criticism of Lecroy's post. If you feel his experience is not typical, then feel free to say so, but certainly you have no expectation that he should not express his experience or opinion.

parts, not "closed

amount of time, it is escalated. Once

the issue.

That is your opinion of how the process works. Many people have had different experiences. Often it is not escalated until the customer requests. Overall the experience can be so frustrating that the customer doesn't push very hard to get a real answer and gives up after a few conversations.

Anyone can be in denial about a problem with their company. But that does not make the problem go away. The problem is also not eliminated by comparing yourself to your competition and saying "we are better than they are". It can still be a problem.

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Rick "rickman" Collins

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rickman

Rick,

Here is my 5th try to respond. Maybe I will send it.

See below.

Aust>

doesn't > work, let us (me) know. You

appreciate the slamming of our hotline

I did not shoot him. I merely mentioned that he should try to get support through the normal channels. And if that did not work, to contact the folks who are watching the watchers. And not slam a service that he did not use.

Perhaps in your mind, but to us it is deadly serious, and we deny that your comments are accurate, or truthful. Sure, one can get a bad answer, or a wrong answer, and occasionally an answer that did not meet your timeline; but if that case is closed before you say you are happy, it is cause for dismissal.

OK. Like you said, all opinions are welcome.

I did.

He is free to say anything he wants, as are you.

sells > parts, not "closed cases." If

of time, it is escalated. Once

resolve the issue.

No, that is the way it does work. I helped re-write it. And audit it.

Then let Peter and I know: I want dates, case numbers and names. I want to know of any unhappy customers anywhere. And yes, I would prefer it sent directly, not the newsgroup, so we can research it properly, and get it resolved ASAP.

Uh, that is how it works, the proceedure is that the customer has to say how urgent the matter is AND the time limits have to start getting exceeded.

Haven't met any like that. Perhaps there are those who are so timid they can't use a hotline? The customers that I meet are not shy at all about demanding the best service. And right now, if they don't get the answer, they are likely to be part of the next layoff, so it is hard for me to see how a customer would not make every effort to get their problem resolved.

Reply to
Austin Lesea

doesn't > work, let us (me) know. You

appreciate the slamming of our hotline

through the normal channels. And if that

slam a service that he did not use.

You didn't shoot him with a gun, but you criticized him for "slamming" your service which he *HAS* used and found to be lacking.

comments are accurate, or truthful. Sure,

did not meet your timeline; but if that

I also like the way that I get survey requests on every case, but I have never heard back from anyone when I fill one out and indicate that a case was prematurely closed or the result was otherwise unsatisfactory.

And receive criticism for giving his experiences.

sells > parts, not "closed cases." If

of time, it is escalated. Once

resolve the issue.

But you don't execute it. As far as I am aware you have not monitored any of the cases described here either. I don't believe you are in the chain of command for the hotline. The bottom line is that you feel the hotline works one way and many of us have different experiences. Obviously our experiences are only "in our minds".

know of any unhappy customers anywhere.

research it properly, and get it resolved ASAP.

It is seldom worth an engineers effort to persue a hotline case for more than a couple of days, much less follow up with a bad case. If you want to follow up on poorly handled cases, why aren't the surveys read and responded to?

urgent the matter is AND the time limits

So if a customer does not know that there are levels of support and the person providing the support has run out of ideas, the customer is expected to figure out to ask for a higher level? Sounds pretty silly to me. Once engineers get familiar with support that may be automatic, but I remember my experiences with support and just how long it took me to learn how to navigate the support pathways to try to get to someone who actually knows about the problem.

I have also had the first level of support refuse to let me talk to the engineer who actually knew something about the problem. Instead he insisted that he be my point of contact and that he would relay the information back and forth to the other engineers. Unfortunately this required several relays just to get the question across since the second level support kept believing that the first level was relaying the question wrong.

The bottom line is that many engineers refuse to contact support even when told to. Their experience has led them to feel that the whole process is poor and not worth the effort.

You can believe what you want, but this is what I have found at most of the companines where I have worked. This is not just my opinion, but that of many engineers.

can't use a hotline? The customers that I

they don't get the answer, they are likely

would not make every effort to get their

Yes, I think you are right. The problem is not with the hotline, it is with the customers. Of course the hotline has been designed to provide the best level of support under all conditions and any customer who has less than a fully satifactory experience must have been poorly trained or is suffering from a personality disorder.

Denial is not just a river in Egypt.

Enjoy your boat tour Austin.

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Rick "rickman" Collins

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Reply to
rickman

Interesting. So this is stress-time effect, that causes a degrade in leakage spec ?

What time/uA orders are we talking about here ?

Does this never cause a more drastic point failure ?

Any idea why Lattice quote a MAX of 64 pins at IO MAX voltage stress levels ? (I'm bemused at how the 65th pin knows the state of the other

64 :)

- jg

Reply to
Jim Granville

Jim,

I will try to add to our knowledge below,

Aust> Aust> >

Yes. It is interesting because it does not follow the "accepted" failure mechanisms, and is being studied by many (not at all new, just new to us because it is the first time we have used this particular .25u pmos transistor for 3.3v IO).

In one set of early tests before they improved the process, we saw 6uA in 10 weeks with a peak voltage stress of ~4.5v. The leakage started out in the nA range. Traditional gate breakdown is defined as a 100x increase in leakage, but it is then usually followed by a complete gate breakdown. The leakage stopped increasing.

Not in the testing we did. That is what we found strange, and led to a reading of some of the more obscure papers on voltage stresses in the public literature.

"Defect generation and breakdown of ultra-thin silicon dioxide induced by substrate hot-hole injection" by Eric M Vogel, Journal of Appplied Physics, V90, N5, 1 September, 2001....as one example of bedtime reading. We concluded that the mechanism described by this paper was NOT what we saw, but then, it wasn't any of the other ones folks know about, either.

Baking the device at a high temperature also did not make the device recover (as would be expected from hot electron damage, for example).

There is no agreement on how to spec this: the area under stress (number of IOs) and temperature figure prominently in the models, but had virtually no effect in the tests we conducted. Now, of course, we have to stress it enough to see an effect (in our limited lifetimes), and one can say with some confidence that such a stress is not going to lead to the actual failure mechanism, but may be causing a new, and artifical failure mechanism. Thus, we combine the older techniques and models, with the latest data and guesses, and error on the side of extreme caution so that we can state that if you do not exceed the abs max numbers, the part lives it regular life.

So, 64 IOs may be just under the 15 or 20 year life projection model limit, and

65 IOs may be just over the limit in the model. Our experience was that the number of IOs under stress did not make a measurable difference. I agree that it is pretty hard to imagine that having a next door neighbor with a hot plate increases your chances of burning down your house, but it does make sense that overall, the more devices you have under stress, the sooner one would expect a failure........even if we did not see that in our testing.

The most recent tests did allow us to relax the bank requirements for V2P, so now all banks may operate at 3.3V, and it will not affect the lifetime nor the reliability of the part (as opposed to the original banking restrictions).

It could be that they have not seen the same results in their testing from their fab? Turns out this is very tricky stuff, and implants, layout, etc affects the performance of these devices under these extrememly high field stress conditions. There is a magic recipe that one finds, and then sticks with it (just like any other IC process).

Reply to
Austin Lesea

it

Yes, I'm sure it's some arbitrary FIT number, or could be some test equipment limit :) - but it does raise the eyebrows ....

now

their

the

Thanks, interesting summary.

I recall seeing a note from Philips research a couple of years ago, about a breakthrough in high voltage devices (> 100V) in (IIRC) 0,5u process. Seems what they found was thinner worked better, the opposite of what E field stress would suggest, and they concluded it was because the 'loose electrons' has less time to accelerate, and so had less energy with which to do serious damage :) Does show there is no substitute for bench tests...

-jg

Reply to
Jim Granville

excursions are, an be sure they stay

will get the "final word" from the

Reply to
lecroy

Surely as hard as you Xilinx guys pushed simulation as the answer for this, you would know the details of the S3 models. Are you looking into it? Is the part just to new and there is no information available at your level?

Reply to
lecroy

No one has responded to my posting here. This is not the sort of question you can expect a good answer from by the hotline. So unless my local rep can give me some straight talk, I will assume that the IBIS models are still very preliminary and not of any real value for simulation yet. BTW, I am having breakfast with my rep and sales person today. We'll see what they have to say about the IBIS models and the partial reconfiguration issues.

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rickman

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