Hi I have two questions regarding Xilinx designs.
[1] How do I identify which paths the static timing analyzer considers to be unconstrained? This has been an ongoing, frustrating task for me. I am an extreme advocate of synchronous design, and to discover that I have 97.3% constraint coverage is disconcerting. That means 2.7% are unconstrained. Clearly the tool has identified these paths, and if there was a way to display them, this would be helplful in isolating problem areas.
[2] Where does Xilinx post rules for treating the multiple clock outputs of DLLs as synchronous? From various postings to the newsgroup, I get the impression that an clk0 and clk divide by 2, should not be treated as synchronous, but either there is a small phase offset which precludes the assumption of edge alignment, or the PAR/TRC tools can not handle setup/holdtime from the two domains. However, I have not read any formal limitations placed on these outputs appearing in either data sheets or application notes.
-- Regards, John Retta
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