I trying to integrate an IP block from a client and it has a ton of clock crossing, most of which are probably OK. Up to now, I've run the Xilinx tools in an iterative mode - set constraints, run Translate, Map, P&R, then look at the timing report to find
*some* unconstrained paths.Is there a Xilinx tool that will look at the Xst output and the UCF file and report the unconstrained paths without going through the time required to run (and rerun) Translate, Map, PAR?
Thanks!
John Providenza
Maybe. For a clean fix, consider using a separate module for each clock domain and run STA on those. Then use "known good" synchronization techniques between the modules.
-- Mike Treseler
Mike -
The IP comes from a client - I can't modify the code to that extent. They control the hierarchy and it's a mess. Hence the need for the unconstrained report.
John P
A previous post >Nico Coesel wrote:
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My local FAE has suggested doing a post-Map but pre-PAR timing extraction. I'll give that a try tomorrow.
John P
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