I have the standard sort of circuit from the Xilinx App note driving an off chip clock:-
Main clock comes onto chip through an IBUFG to CLKIN of the DLL
CLK0 from the DLL is fed off the chip through an OBUFT.
The output of the OBUFT, which is on a global clock pin, is fed back in via an IBUFG to form CLKFB of the DLL.
This seems to work fine.
Main clock to output clock delay is constrained to
off
via
to
Thinking about it further, even if the delay was 10ns, the DLL should have removed it. I would have expected very little delay from the main clock to the output of the OBUFTs, wether or not I have the BUFG in the way. Seems OK without the BUFG, but not with.
This may not address your problem, but...
Just a thought, I like using the DDR mechanism to get clocks out of the FPGA. I've done source-synchonous outputs on V2 up to 200MHz with great success. Besides, it's free, since the IOB flip-flop's involved would not otherwise be used.
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian
To send private email:
0_0_0_0 snipped-for-privacy@pacbell.net where "0_0_0_0_" = "martineu"
off
via
to
Howdy Ken,
I recall discovering the same thing on a design 18 months or so ago, although I don't remember the difference being 5 ns (between BUFG and not)! I believe the problem is that even though you are driving the net with a BUFG, it gets off the global clock net immedately and uses normal routing to get to non-CLK IO's.
This is the reason you'll hear people talking about using a DDR scheme to generate a clock at the IOB. Anything less than that, and you are subject to an inexact amount of routing delay and skew. The next best thing to using DDR is using MAXDELAY and MAXSKEW constraints.
See
Good luck,
Marc
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.