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Maplib Error 661.

Hi, I am getting this error while implementing my design with the xilinx ise tool

Using target part "2v6000ff1152-4". Mapping design into LUTs... ERROR:MapLib:661 - LUT4 symbol "ins_part0/ins_partition_0/Partition_0_1_Multiclock_event_out127" (output signal=fpga0_top_multiclock_event0_out_OBUF) has input signal "evtDetect5" which will be trimmed. See the trim report for details about why the input signal will become undriven.

Error found in mapping process, exiting... Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.

If anybody have solved this, waiting for their positive response. Regards Jitendra

Reply to
Jiten
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I once saw something like this. It turned out it was due to the design being too big for the part. Don't know if this is your problem though.

Cheers, Jon

Reply to
Jon Beniston

I had a similar kind of error, when I was using a wrong netlist..Basically in my source, I had a component with few ports declared as INOUT, but the netlist just had OUT's. So MAP was failing giving me this error. After I had the correct netlist, I never got this error.. Hope this helps...

-- Parag

Jiten wrote:

Reply to
beeraka

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