Xilinx ISE Warning: FF/Latch <> is unconnected in block <>

Hi there,

I created a CPLD design which works perfect in simulation, but does not work in hardware. There are many warnings from the Xilinx ISE looking like

WARNING:Xst:1291 - FF/Latch is unconnected in block .

or

WARNING:Xst:1710 - FF/Latch (without init value) is constant in block .

These come up only in the Low Level Synthesis processing step. There is one relevant solution record on the Xilinx website (see

created, but the output is never connected or the signals or logic it drives have been trimmed. Check the XST log for messages such as the following to find signals that have been trimmed out of the design:

"WARNING:Xst:646 - Signal is assigned but never used."