Problems with ISE logic optimization

Hello, I'm trying to implement a simple delay line for a 1MHz clock with an even number of inverter cells but the Synthetizer/Mapper doesn't work!! I think the logic optimizer is simplifying my even inverter cells in a short circuit... Wich kind of options can I use for the Xilinx tools? I'm using ISE7.1 and ISE8.1 with a Spartan3 device. How can I implement a simple delay line with about 500ps of delay in a FPGA? Thanks a lot!!

Reply to
dmos
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I think this is a very bad approach. Gate delay times depend greatly on temperature, so your 500 ps may be almost anything, but most of the time they will not be 500 ps.

In fact, the propagation time from G to Y in a CLB varies from 530 to

610 ps, which is always more than what you want.

Do you really need such a fine delay? It is only 0.05%!

Regards

Zara

Reply to
Zara

It's correct, it's a very bad approach, but I think it's the simplest... The delay depends on temperature, but for my application, is not so important the absolute value of this delay if it's less than 1ns. It's more important that two contiguous delay cells have the same delay.

Regards

Reply to
dmos

## >Hello, I'm trying to implement a simple delay line for a 1MHz clock ## >with an even number of inverter cells but the Synthetizer/Mapper ## >doesn't work!! I think the logic optimizer is simplifying my even ## >inverter cells in a short circuit... ## ## ## I think this is a very bad approach. Gate delay times depend greatly ## on temperature, so your 500 ps may be almost anything, but most of the ## time they will not be 500 ps. ##

Probably the best is to use LUT1/2/3/4 and (R)LOCs to ensure that the buffer/inverter/logic function is synthesized as one CLB only.

Zara

Reply to
Zara

Also make sure the routing resources are locked too. DIRT (direct routing) strings may help.

HTH, Jim

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Reply to
Jim Wu

I've resolved the problem using LUT1 and (R)LOC constraints for direct routing!! Thanks a lot for the suggestions!!!

Daniel

Reply to
dmos

This is exactly what the synthesizer is supposed to do. You need to instantiate hard macros. You can generate the macros using the FPGA editor and than instantiate them as black boxes in your HDL. As most of the delay in an FPGA is in the routing you also need to manually place the macros. Probably the least sensitive delay in an FPGA is the carry logic. It is a lot faster than

500ps but this allows you to calibrate your delay in approximate 50ps steps. Just have a reference line that measures how far a signal can go in one clock cycle and based on that measurement decide, where you want to tap your delay line.

See this paper for an example:

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There is also a paper about people who calibrated an FPGA delay line by modulating the power supply but I can not find it at the moment.

On the other hand: Why not buy a commercial TDC?

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Kolja Sulimma

Reply to
Kolja Sulimma

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