Hello, I'm trying to implement a simple delay line for a 1MHz clock with an even number of inverter cells but the Synthetizer/Mapper doesn't work!! I think the logic optimizer is simplifying my even inverter cells in a short circuit... Wich kind of options can I use for the Xilinx tools? I'm using ISE7.1 and ISE8.1 with a Spartan3 device. How can I implement a simple delay line with about 500ps of delay in a FPGA? Thanks a lot!!
- posted
17 years ago