My design is mixed, Microblaze in VHDL and the application in verilog with CORE memory FIFOs and Dual Ports. I used CORE Gen for the memory blocks. XPS cannot link my memory blocks when doing a bit stream generate. If I do a place and route in ISE for just my app (verilog) it runs just fine. Anybody else having this problem?
Thanks
What do you mean by "XPS cannot link my memory blocks when doing a bitstream generate" ?? Did you create a pcore from your verilog core ? You can also try instantiating the XPS project as a sub-module within ISE.
Amit
Jerry wrote:
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