Peripheral Trouble!

Hello,

I am using the xilinx virtex II development board xupv2p. I have built a expansion board that connects to the high speed expansion port, an delivers information from a camera. In ISE, I have produced what I thin is a working piece of vhdl to synchronise the camera data (there will be data sets incoming) to the FPGA clock.

What I would like to do is just read out this incoming data so I can chec it. My idea was to use a microblaze processor - I will need one to do som processing at a later stage, and just do a printf to write the data t hyper-terminal.

I used the create / import peripheral wizard, and have been hacking th user_logic file to incorporate my synchronization design. I am a bi unsure of ports though - do I have any user ports - are these the inpu pins??? I have altered the UCF file to assign the pins of the expansio port to my inputs in my vhdl file. Should I write this data to a slav register??

Then in my C file, is it just a simple read and printf procedure.

Any help / ideas I'd be grateful,

Thanks

Marc.

Reply to
MJ Pearson
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Hi, I don't know if I have understood your point but it seems to me that you want to print data coming from a camera.

If so, you should create a peripheral (like you have already done) with some SW registers. This registers are the interface between the peripheral and the microcontroller. The additional ports of your peripheral will be the interface between the peripheral itself and the camera. So your IP, once acquired the desired data, should write something to a register so that you can read it from the microprocessor. Probably you also need to write a simple driver (in C language) to find if there's someting new in the register, read the register and so on (the driver isn't strictly necessary). Googoling around you'll find all the details.

Hope this help a little.

Andrea

Reply to
Andrea05

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Thanks for the reply.

Have got (a little) further with this....

I have made a number of external input ports for the inputs from m camera(s). I have altered the ucf file, mpd, mhs...

I used the create / import peripheral wizard, and as mentioned hav altered the user_logic.vhdl file. Do I need to map my external ports o the peripheral .vhdl file (created by the wizard)?

I get an error when I build the netlist:

ERROR:MDT - HDL synthesis failed! INFO:MDT - Refer to C:\MATLAB\R2006a\work\edkStuff\periphWizard\synthesis\camtoleds_0_wrapper_xst .srp for details

ERROR:MDT - platgen failed with errors!

Looking at the .srp file :

Formal CAM1_I_0 of entity with no default value must be associated with a actual value.

CAM1_I_0 is an input port in my user logic .vhdl file. Which I have (thin I have) mapped to an external pin via my ucf file:

UCF snippet: NET "CAM_IN_0_pin" LOC = "AE5"; NET "CAM_IN_0_pin" IOSTANDARD = LVTTL;

MHS: PORT CAM1_I_0 = CAM_IN_0

.mpd: PORT CAM1_I_0 = "", DIR = I

Sorry if all this sounds pathetic, I have no idea how to fix that error, am a bit lost!!

Reply to
MJ Pearson

You may want to look at the "Platform Specification Format Reference Manual" a.k.a. UG131. It is included with EDK and is located at $EDK/ doc/psf_rm.pdf. Take a look at the section on ports, and the key word IOB_STATE.

In your .mpd, you have not specified the IOB_STATE, so it will default to INFER, which will cause EDK to instantiate its own IBUF in the top level VHDL file. If you had an IBUF already in your code, this would cause a problem. I don't know if it would cause the problem you are seeing. If that is not it, read through the psf_rm, it describes how all the EDK files work.

Regards,

John McCaskill

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Reply to
John McCaskill

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