Hello I'm working on Xilinx virtex II Pro FPGA kit.I generated netlist for OR gate using JHDL, with a1 and a2 being inputs, and op being the output. I also created the following User constraint file: (not sure if the given constraints are right!)
NET "a1" LOC="AC4"; NET "a2" LOC="AC3"; NET "op" LOC="AA6";
Using Xilinx ISE, i gave the command: (i'm particular abt not using the GUI, as i need to call the cmds programmatically) ngdbuild -p xc2vp30-ff896 -uc or_gate.ucf or_gate.edn
Here i get the following warning: WARNING:NgdBuild:483 - Attribute "LOC" on "op" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute. WARNING:NgdBuild:483 - Attribute "LOC" on "a2" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute. WARNING:NgdBuild:483 - Attribute "LOC" on "a1" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.
And subsequently, when i tried to map using the command map or_gate.ngd ( the ngd file created in the above ngdbuild step) i get the following error. ERROR:Pack:198 - NCD was not produced. All logic was removed from design. This is usually due to having no input or output PAD connections in the design and no nets or symbols marked as 'SAVE'. You can either add PADs or 'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in the mapper.
Please guide me as to how i can correct these errors. Is there some specific tutorials available for writing user constraint files and to readback the logic from FPGA and find if they are correct, by some means? Thanks Quad
P.S: I'm pasting the edif file (or_gate.edn) generated by JHDL for your reference
(edif evolution2_ckt (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2007 2 10 10 28 36) (program "BYU-CC's JHDL-EDIF netlister by Peter Bellows and Eric Blake" (version "0.3.45")))) (library evolution2_ckt (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit CAPACITANCE)))) (cell (rename or2 "or2") (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port i0 (direction INPUT)) (port i1 (direction INPUT)) (port o (direction OUTPUT)) ) )) (cell (rename orX_2 "orX_2") (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port (array (rename i "i[1:0]") 2) (direction INPUT)) (port o (direction OUTPUT)) ) (contents (instance or2 (viewRef view_1 (cellRef or2)))
(net (rename i__0__ "i") (joined (portRef i0 (instanceRef or2)) (portRef (member i 0)))) (net (rename i__1__ "i") (joined (portRef i1 (instanceRef or2)) (portRef (member i 1)))) (net (rename o "o") (joined (portRef o (instanceRef or2)) (portRef o))) ) )) (cell (rename orX_g_1 "orX_g_1") (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port in1 (direction INPUT)) (port in0 (direction INPUT)) (port out (direction OUTPUT)) ) (contents (instance orX (viewRef view_1 (cellRef orX_2)))
(net (rename in1 "in1") (joined (portRef (member i 0) (instanceRef orX)) (portRef in1))) (net (rename in0 "in0") (joined (portRef (member i 1) (instanceRef orX)) (portRef in0))) (net (rename out "out") (joined (portRef o (instanceRef orX)) (portRef out))) ) )) (cell (rename evolution2_ckt "evolution2_ckt") (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port a1 (direction INPUT)) (port a2 (direction INPUT)) (port op (direction OUTPUT)) ) (contents (instance orX_g (viewRef view_1 (cellRef orX_g_1)))
(net (rename op "op") (joined (portRef out (instanceRef orX_g)) (portRef op))) (net (rename a2 "a2") (joined (portRef in1 (instanceRef orX_g)) (portRef a2))) (net (rename a1 "a1") (joined (portRef in0 (instanceRef orX_g)) (portRef a1))) ) )) ) (design ROOT (cellRef evolution2_ckt (libraryRef evolution2_ckt))) )