par problems with modular design for partial reconfiguration

is it becuase the area is way too big for your codes?

i had one pexerience when my reconfiguration module is 58 slices, and the area allocated to it is 3072 slices. it took over two hours to route that small module...fixed module is 3000+ slices in an area of 30000 slices, and it took 10 minutes only...In the trial synthesis, I will use an xc2v2000 to replace my xc2v6000 and see how it works...

I also found that, Route Phase 1 takes most of the time, while other 8 stages takes only a fraction of the total time...

In the tutorials I created at home, the slice numbers are 759(fixed) out of

1536, 292/338(reconfigurable) out of 1,536, the whole flow, from synthesis to assembly, only took 20 minutes...

Hope you could share your experiences after you finished the project...

Best Regards, Kelvin...

It is better to line up your muxes vertically. That is how the configuration memory is set up. If you put your muxes all across the top, for example, You will have to reload the whole device. If you line them up along a set of columns then you only have to reconfigure the columns (not counting any routes that go across horizontally).

Steve

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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

wel actually it is! the muxes hardly take up 5-10 SLICEs whereas i give an area constraint that spans the entire column! I' trying to pack in more l;ogic into this column and will see what happens from there on.

Yeah that was my experience as well..wonder how the router works ?

So some runs of the router on certain mux columns in my design takes seconds while the rest of the runs take about half an hour.. i think i should try running them as separate designs with the same area constraints without modular design flow to see if it takes just as much time to do the routing..

certainly...

nachiket.

I'm working on creating new constraint files to nail the muxes down to specific slices within the column. hope it works..

Depending on your

So the placer seems to be finishing off its job in abt 10 seconds. I still dont understand how badly can a placer mess up on a design this simple!...8 2:1 muxes?

Also, you'll want to organize them as a column

point noted.

thanks, nachiket.

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

ok, i am trying to get the module placed manually but and am encountering the following problems in map:-

1. if i try to place all the components in the module (i have a structural code with xilinx library components) i get an error in map saying "active module missing". so when to get arond that if i remove even a single constraint from the ucf, the active module magically reappears. the par still fails saying unroutable design with 38 nets.
2. if i try to assign constraints to internal nets that connect modules together using the PIN constraint (is this really necessay?....the modular design doc. refers to these signals as pseudo logic in the ucf). i did seem to get better routing results with only

9 unrouted nets as against 38 unrouted in case.(1)

i still am completely at a loss to understand why a design with 16 2:1 muxes with 16 flops given an area constraint of half a column of width

4 SLICEs struggles with routing. also, when doing modular design, does the router try to route the upper level signals?..because the router quotes a large number of 134 unrouted nets to start off for the above design. how does the modular design methodology deal with having to route the top-level signal like clk,reset of fpga-io?..i sure hope it doesn't bother itself with those signals while routing a module.

regards, nachiket.

guarantee it ain't