Hi everyone,
why doesn't this synthesize:
architecture Behavioral of datacontroller is type states is std_logic_vector(4 downto 0); constant stateStart : states := "00001"; constant stateWait : states := "00010"; constant stateTrigger : states := "00100"; constant stateHold : states := "01000"; constant stateRead : states := "10000";
signal holdoff : std_logic; signal holdoff_counter_enable, holdoff_counter_reset : std_logic;
component counter19bit Port ( clk, ce, reset : in std_logic; preset : in std_logic_vector(19 downto 0); c : out std_logic; q : out std_logic_vector(18 downto 0)); end component; begin [SNIP]
It's directly taken from the book "VHDL made easy". I'm using Xilinx Webpack 6.3i!
Thanks Preben Holm