Hi,
I've been working on Virtex 4 with a DDR2 controller for about 1 year now and it works fine. The controller is based on MiG generated controller that we modified. The changes were some little bug fixes and changes in the user interface. This controller uses the ISERDES / OSERDES so that at the end, the physical interface of DDR2 is 8 bits at 250 MHz and the user interface internally is 32 bits at 125 MHz.
For Virtex 5 there doesn't seem to be such a design yet (with control and user interface running at half the frequency) so we just tried to use the one we used on virtex 4. Personnaly I don't see why this would not work. The control part is pure HDL and the IO part uses components that are present in both V4 and V5 and I couldn't see any difference in them.
But unfortunatly we didn't manage to make it work. My colleagues worked on it part of last week and I worked on it theses last 3 days without success. The simulation is OK but on the physical board it just doesn't calibrate (i.e. it doesn't manage to do a single good read even when trying all possible IDELAY values for DQ/DQS delaying).
Does any one know of any differences between V4 and V5 that would make it un-usable ? Or particular points I should pay attention to ?
Thanks,
Sylvain